应该抓两种方法并使用DCM作为25MHz信号吗？

我有一个由50MHz晶体驱动的电路，我通过DCM加倍。
在100MHz之外，我需要一些其他时钟来驱动较慢的电路部分。
其中一个是用于VGA同步的25MHz时钟。
最初我有一个分频器电路，它产生25MHz“时钟”信号，周期为50/50。
我就像主时钟那样使用那个信号：
如果rising_edge（clk50mhz）那么
一切都工作正常，但我正在阅读一些其他代码，其中使用“启用”信号。
因此，25MHz使能信号仅在每4个时钟的1个主时钟周期有效，我会像这样使用它：
如果rising_edge（clk）那么
如果en50mhz ='1'则
在更改了我的所有代码之后，现在综合报告我的电路将以70MHz的频率运行，而之前的频率为104MHz，而我的VGA输出现在搞砸了。
在我尝试制作VHDL工作的“启用”版本之前，我想知道哪种更好的做法？
或者，我应该抓两种方法并使用DCM作为25MHz信号吗？
那么，我应该：
1.使用计数器从主时钟（来自单个DCM的输出）导出“时钟”信号？
2.从主时钟发出“启用”信号，这些信号仅对主时钟的单个时钟有效？
3.使用单独的DCM来获取我需要的所有信号？
谢谢，
马修



以下为原文

I have a circuit driven by a 50MHz crystal which I'm doubling via a DCM.  Out of that 100MHz, I need a few other clocks to drive slower parts of the circuit.  One of them is a 25MHz clock for the VGA sync.

Originally I had a divider circuit that was making a 25MHz "clock" signal with a 50/50 period.  I was using that signal just like the main clock:

if rising_edge(clk50mhz) then

Everything was working fine, but I was reading some other code where an "enable" signal was used instead.  So, the 25MHz enable signal is only active for 1 main clock tick every 4 ticks, and I would use it like this:

if rising_edge(clk) then
  if en50mhz = '1' then

After changing all my code, synthesis now reports the max my circuit will run at is 70MHz vs the 104MHz I had before, and my VGA output is now messed up.

Before I try to make the "enable" version of my VHDL work, I'd like to know which is a better practice?  Or, should I scratch both methods and use a DCM for the 25MHz signal?

So, should I:

1. Derive "clock" signals from the main clock (output from the single DCM) with counters?

2. Make "enable" signals from the main clock that are only active for a single tick of the main clock?

3. Use individual DCMs for all the signals I need?

Thanks,
Matthew