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[问答]

JESD204不允许生成比特流

我们购买了两个评估套件:ZC706和ARDV9371,将它们连接在一起。
现在我们要修改从ADI获得的FPGA代码。
我已经安装了ZC706的许可证,后来又安装了JESD204的评估许可证(见附件)。
现在,当我尝试编译时,只有比特流生成失败:
[Common 17-69]命令失败:此设计包含一个或多个不允许生成比特流的单元:i_system_wrapper / system_i / axi_ad9371_tx_jesd / inst / i_system_axi_ad9371_tx_jesd_0(jesd204_v7_0_1_topparameterized1)
i_system_wrapper / system_i / axi_ad9371_rx_os_jesd / inst / i_system_axi_ad9371_rx_os_jesd_0(jesd204_v7_0_1_topparameterized0)
i_system_wrapper / system_i / axi_ad9371_rx_jesd / inst / i_system_axi_ad9371_rx_jesd_0(jesd204_v7_0_1_top)
如果添加了新的IP核许可证,为了获取新许可证,需要通过在比特流生成之前重置和重新生成IP输出产品来更新当前网表。
我已经四处搜索,并尝试了https://www.xilinx.com/support/answers/58758.html中提出的解决方案,但“重置输出产品”根本无法使用。
我尝试过Vivado 2017.2和2016.2(后者可能更适合该项目)。
我无法以任何方式重新生成IP。
谢谢

以上来自于谷歌翻译


以下为原文

We have bought two evaluation kits: ZC706, and ARDV9371, to connect them together. Now we want to modify the FPGA code obtained from ADI. I have installed the licence for the ZC706, and later on the evaluation licence for the JESD204 (see attached). Now when I try to compile, only the bitstream generation fails with:

[Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted: i_system_wrapper/system_i/axi_ad9371_tx_jesd/inst/i_system_axi_ad9371_tx_jesd_0 (jesd204_v7_0_1_topparameterized1)
i_system_wrapper/system_i/axi_ad9371_rx_os_jesd/inst/i_system_axi_ad9371_rx_os_jesd_0 (jesd204_v7_0_1_topparameterized0)
i_system_wrapper/system_i/axi_ad9371_rx_jesd/inst/i_system_axi_ad9371_rx_jesd_0 (jesd204_v7_0_1_top)
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.

I have searched around, and tried the solution proposed in https://www.xilinx.com/support/answers/58758.html, but "Reset Output Products" is simply not available to me. I have tried with Vivado 2017.2 and 2016.2 (the later is possibly better suited for the project). I am not able to regenerate the IP in any way.

Thank you

回帖(16)

石俊梅

2019-1-2 15:04:42
Hitcachat@metraware.com
如果右键单击层次结构或IP源窗口中的IP XCI文件,您将看到“重置输出产品”选项。
如果你找不到它,你能告诉我们这个菜单的截图吗?
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以上来自于谷歌翻译


以下为原文

Hi tcachat@metraware.com
 
If you right click on the IP XCI file in hierarchy or IP sources window, you will see the "reset output products" option. Can you show us a screenshot of this menu if you dont find it? 
Thanks,
Deepika.
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胡燕珍

2019-1-2 15:21:43
Hitcachat@metraware.com
>>我已经四处寻找,并尝试了解决方案:http://www.xilinx.com/support/answers/58758.html,但“重置输出产品”根本无法使用。
当你说复位输出产品不适合你时,你的意思是什么?
您只需在设计层次结构源窗口中单击JESD IP,右键单击并重置输出产品,然后生成输出产品。
如果它没有帮助,那么尝试从头开始创建项目,让我们知道结果。
问候
罗希特
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以上来自于谷歌翻译


以下为原文

Hi tcachat@metraware.com
 
>>I have searched around, and tried the solution proposed in https://www.xilinx.com/support/answers/58758.html, but "Reset Output Products" is simply not available to me.
 
What do you mean when you say reset output products is not available for you? You need to simply click on JESD IP in the design hierarchy source window, right click and do reset output products followed by generate output products. 
 
Still if it didn't help then try creating the project from scratch and let us know the results.
 
Regards
Rohit
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Regards
Rohit
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韩俊

2019-1-2 15:30:32
谢谢。
附件是一个屏幕截图。
“重置输出产品......”根本不可用(屏蔽?)。
它与Vivado 2017.2类似,只是IP被锁定(红锁)。

以上来自于谷歌翻译


以下为原文

Thank you.
Attached is a screen shot. The "Reset Output Products..." is simply not available (shielded ?).
 
It is similar with Vivado 2017.2, except that the IP is locked (red lock).
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李铃华

2019-1-2 15:42:39
我可以正确看到复位输出。
你能检查你的许可证状态吗?
谢谢和RegardsBalkrishan -----------------------------------------------
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以上来自于谷歌翻译


以下为原文

I can see reset output correctly . Can you check your license status
Thanks and Regards
Balkrishan
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