在Kintex 7中找到具有不同IODELAY组约束的相同形状的IODELAY单元格

我已成功级联IDELAYCTRL模块，以便在Xilinx版主和员工的帮助下增加分接头延迟，尤其是@syedz和@marcb。
为了下一步，我在N Path of Differential Buffer中整合了两个以上的IDELAYCTRL模块。
在实施过程中，我得到了以下DRC错误：
[DRC PLIDC-5]具有冲突组的IDELAYCTRL IODELAY形状：找到具有不同IODELAY组约束的IODELAY单元格，形状相同。
IODELAY单元及其受限于此形状的组是：'mb_subsystem_i / Slave_Pre_iDelay / inst / pins [0] .idelaye2_bus：mb_subsystem_pre_idelay_0_group''mb_subsystem_i / pre_idelay / inst / pins [0] .idelaye2_bus：mb_subsystem_cascaded_Pre_Delay'
带有IODELAY组的IODELAYCTRL组是：
最后IODELAY_GROUPsSr.No.IDELAYCTRLIODELAY_GROUP1mb_subsystem_i / axi_ethernet_0 /安装/ MAC /安装/ tri_mode_ethernet_mac_idelayctrl_common_itri_mode_ethernet_mac_iodelay_grp2mb_subsystem_i / mig_7series_0 / u_mb_subsystem_mig_7series_0_0_mig / u_iodelay_ctrl / u_idelayctrl_200MB_SUBSYSTEM_MIG_7SERIES_0_0_IODELAY_MIG03mb_subsystem_i / Post_iDelay /安装/ delayctrlmb_subsystem_cascaded_Post_delay4mb_subsystem_i / pre_idelay /安装/ delayctrlmb_subsystem_cascaded_Pre_DelayAdditional IODELAY GROUPS5mb_subsystem_i / Slave_Post_iDelay /安装/ delayctrlmb_subsystem_Post_iDelay_0_group6mb_subsystem_i / Slave_Pre_iDelay /安装/ delayctrlmb_subsystem_pre_idelay_0_group
请帮助我解决这个问题。
问候，
穆赫辛



以下为原文

I have successfully cascaded the IDELAYCTRL modules to increase the tap delays with the help of Xilinx Moderators and Employees, especially @syedz and @marcb. For the next step, i have integarted two more IDELAYCTRL Modules in the N Path of Differential Buffer. During implementation,i got following DRC Error:

[DRC PLIDC-5] IDELAYCTRL IODELAY shape with conflicting groups: Found IODELAY cells with different IODELAY group constraints in the same shape. The IODELAY cells and its group constrained to this shape are: 'mb_subsystem_i/Slave_Pre_iDelay/inst/pins[0].idelaye2_bus : mb_subsystem_pre_idelay_0_group' 'mb_subsystem_i/pre_idelay/inst/pins[0].idelaye2_bus : mb_subsystem_cascaded_Pre_Delay'

The IODELAYCTRL Groups with IODELAY Groups are:

Final IODELAY_GROUPs
Sr.No.	IDELAYCTRL	IODELAY_GROUP
1	mb_subsystem_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i	tri_mode_ethernet_mac_iodelay_grp
2	mb_subsystem_i/mig_7series_0/u_mb_subsystem_mig_7series_0_0_mig/u_iodelay_ctrl/u_idelayctrl_200	MB_SUBSYSTEM_MIG_7SERIES_0_0_IODELAY_MIG0
3	mb_subsystem_i/Post_iDelay/inst/delayctrl	mb_subsystem_cascaded_Post_delay
4	mb_subsystem_i/pre_idelay/inst/delayctrl	mb_subsystem_cascaded_Pre_Delay
Additional IODELAY GROUPS
5	mb_subsystem_i/Slave_Post_iDelay/inst/delayctrl	mb_subsystem_Post_iDelay_0_group
6	mb_subsystem_i/Slave_Pre_iDelay/inst/delayctrl	mb_subsystem_pre_idelay_0_group

Please Help me out in this Problem.

Regards,
Mohsin