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张琳

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[问答]

使用PSoC5实现定制锁相环(PLL)

你好,
下面提供的是模拟锁相环(PLLYSCM)的自定义实现。
器件采用相位频率检测器(PFD)作为相位比较器和基于开关电容Δ∑调制器的压控振荡器。低通滤波器只需要很少的外部电容器和电阻器。PLLYSCM可以锁定数字信号,产生同一频率的一个输出,另一个乘以频率,两者都与输入相位对齐。该组件被设计为在低频(10Hz~10kHz)下工作,主要目标是跟踪交流电源线(50-60Hz)。
组件作为RMS检测项目的一部分开发。它可以用于频率倍增,正交生成,电机控制,吉他音效等。
使用CY8KIT-059 PSOC5原型试剂盒进行了测试。提供了几个演示项目。
主要特点:
用II型鉴频器实现模拟锁相环。
使用第一阶Δ∑调制器作为VCO。
初级输出在频率和相位上都是锁定的。
倍频的二次输出。
输出用于可选的锁定检测。
不消耗CPU。
附加存档包含组件库、组件数据表和几个用于PSoC5的演示项目。请阅读Read M.TXT中的安装说明。
所提供的组成部分是,没有负债。它可以自由使用和修改。
YouTube视频显示组件在行动:
自定义锁相环(PLL)演示使用PSOC5微控制器-YouTube
当做,
奥迪赛1
拉链
3.4兆字节
邮编
2.1兆字节
PLLY-SMCMV0.0A.PDF
1.8兆字节
拉链
872字节

以上来自于百度翻译


     以下为原文
  Hi,

Provided below is a custom implementation of analog Phase-Locked Loop (PLL_scm).

Component implements Phase-Frequency Detector (PFD) as phase comparator and voltage-controlled oscillator based on switched-capacitor delta-sigma modulator. Only few external capacitors and resistors required for low-pass filter. PLL_scm can lock to digital signal, producing one output of the same frequency, and another one of multiplied frequency, both are phase-aligned with the input. The component was designed to operate at low frequencies (10Hz–10kHz), with primary goal of tracking AC power lines (50-60 Hz).

Component was developed as part of RMS detection project. It can be useful for frequency multiplication, quadrature generation, motor control, guitar sound effects, etc.
It was tested using CY8KIT-059 PSoC5 prototyping kit. Several demo projects are provided.

Component Major features:
   Implements analog PLL using Type-II Phase Frequency Detector.
   Uses 1st-order delta-sigma modulator as VCO.
   Primary output is locked in both frequency and phase.
   Secondary output for multiplied frequency.
   Output for optional lock detection.
   Does not consume CPU.

Attached archive contains component library, component datasheet and several demo projects for PSoC5. Please read installation instructions in the readme.txt.

The component provided as-is, no liabilities. It is free to use and modify.

YouTube video showing component in action:
Custom Phase Lock Loop (PLL) demo using PSoC5 microcontroller - YouTube

regards,
odissey1




回帖(2)

黎菁菁

2018-11-7 17:16:08
是否可以输入一个32668 kHz时钟(DS323)并获得1048 57 6MHz(32×327 68)来与DDS32一起使用?

以上来自于百度翻译


     以下为原文
  Is it possible to input a 32,768kHz clock (DS3231) and get 1,048576MHz (32x32,768) to use with DDS32?
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张琳

2018-11-7 17:23:33
引用: 60user22 发表于 2018-11-7 17:02
是否可以输入一个32668 kHz时钟(DS323)并获得1048 57 6MHz(32×327 68)来与DDS32一起使用?

以上来自于百度翻译

乔吉斯尔瓦,
对于这种类型的PLL,1 MHz太高。该组件使用基于Delta∑调制器的非常特定的VCO,该调制器被优化用于低频操作(<100kHz)。
我看到几个选项,以达到1.048576兆赫。
1。使用XTAL(24 MHz)或外部时钟作为稳定参考,以及DDS32分量以获得精度约为0.01 Hz的期望频率。但这不是真的锁。参见第15页
DDS24:24位DDS任意频率发生器组件
2。可以使用不同类型的VCO修改PLL组件,优化为在1 MHz范围内工作。基本上,使用PFD示意图和除法器,并添加自己的VCO。我尝试了几个VCO示意图,能够达到30兆赫,但没有时间把它一起作为一个组成部分。你的优点是希望的频率范围非常窄,所以你可以使用简单的1 MHz陶瓷谐振器+ 2个电容器,加上变容二极管调谐振荡器频率在1%以内锁定到32×327 68赫兹石英。参见示例图片。
三。作为纯理论方法,应该有一种方法将PSOC5主PLL直接锁定到32 kHz石英。我没有做到这一点,但认为这是可能的一些诡计。
ODISSEY1

以上来自于百度翻译


     以下为原文
  jorgesilva,
1 MHz is too high for this type of PLL. The component uses very specific VCO, based on Delta-Sigma Modulator, which is optimized for low frequency operation (<100kHz).
 
I see several options to get to 1.048576 MHz.
1. Use XTAL (24 MHz) or external clock as stable reference, and DDS32 component to obtain desired frequency with accuracy of about 0.01 Hz. This is not true lock though. See #15 at
DDS24: 24-bit DDS arbitrary frequency generator component
 
2. It is possible to modify PLL component using a different type of VCO, optimized to operate in 1 MHz range. Basically, use PFD schematic and divider and add your own VCO. I tried several VCO schematics and was able to get up to 30 MHz, but had no time to put it together as a component. Your advantage is that desired frequency range is very narrow, so you can use simple 1 MHz ceramic resonator +2 capacitors, plus a varactor diode to tune oscillator frequency within ~1% to lock to 32x32768 Hz quartz. See example picture.
 
   
3. As purely theoretical approach, there should be a way to lock PSoC5 main PLL to 32kHz quartz directly. I have not accomplished that, but think it is possible with some trickery.
/odissey1
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