我正在约束设计的一部分，即作为IP（.ngc）导入，以便关闭设计区域。
根据约束指南：
GROUPGROUP控制逻辑打包到物理组件（即切片）asfollows.CLOSED不允许AREA_GROUP外部的逻辑与AREA_GROUP外部的AREA_GROUP.OPENAllow逻辑内的逻辑组合，以与AREA_GROUP内的逻辑组合。默认值为GROUP
= OPEN.PLACEPLACE控制区域组的RANGE中的资源分配，如下所示.CLOSED不允许放置不是AREA_GROUP成员的comps，而是为不属于AREA_GROUP成员的AREA_GROUP.OPENAllow comps定义RANGE
置于为AREA_GROUP定义的RANGE中。默认值为PLACE = OPEN。
所以，如果我使用以下约束：
INST “A
FPGA_Core0” AREA_GROUP = “pblock_AFPGA_Core0”; AREA_GROUP “pblock_AFPGA_Core0” RANGE = SLICE_X8Y300：SLICE_X35Y349; AREA_GROUP “pblock_AFPGA_Core0” RANGE = DSP48_X0Y120：DSP48_X1Y139; AREA_GROUP “pblock_AFPGA_Core0” RANGE = RAMB18_X0Y120：RAMB18_X2Y139; AREA_GROUP “pblock_AFPGA_Core0” RANGE = RAMB36_X0Y60：RAMB36_X2Y69;
AREA_GROUP“pblock_AFPGA_Core0”GROUP = CLOSED; AREA_GROUP“pblock_AFPGA_Core0”PLACE = CLOSED;
区域内的切片，dsps和ramb不应用于放置或路由其他组件。
但是，在PlanAhead中运行时，其他组件的元素将放置在此范围内。
PlanAhead会忽略我的约束吗？
以上来自于谷歌翻译
以下为原文
I am constraining a part of the design, that is imported as an IP (.ngc), such that the area for the design is closed. According to the constraints guide:
GROUP
GROUP controls the packing of logic into physical components (that is, slices) as
follows.
CLOSED
Do not allow logic outside the AREA_GROUP to be combined with logic inside
the AREA_GROUP.
OPEN
Allow logic outside the AREA_GROUP to be combined with logic inside the
AREA_GROUP.
The default value is GROUP=OPEN.
PLACE
PLACE controls the alloca
tion of resources in the area group’s RANGE, as follows.
CLOSED
Do not allow comps that are not members of the AREA_GROUP to be placed within
the RANGE defined for the AREA_GROUP.
OPEN
Allow comps that are not members of the AREA_GROUP to be placed within the
RANGE defined for the AREA_GROUP.
The default value is PLACE=OPEN.
So if I use the following constraints:
INST "AFPGA_Core0" AREA_GROUP = "pblock_AFPGA_Core0";
AREA_GROUP "pblock_AFPGA_Core0" RANGE=SLICE_X8Y300:SLICE_X35Y349;
AREA_GROUP "pblock_AFPGA_Core0" RANGE=DSP48_X0Y120:DSP48_X1Y139;
AREA_GROUP "pblock_AFPGA_Core0" RANGE=RAMB18_X0Y120:RAMB18_X2Y139;
AREA_GROUP "pblock_AFPGA_Core0" RANGE=RAMB36_X0Y60:RAMB36_X2Y69;
AREA_GROUP "pblock_AFPGA_Core0" GROUP=CLOSED;
AREA_GROUP "pblock_AFPGA_Core0" PLACE=CLOSED;
The slices, dsps, and ramb's within the area should not be used for placement or routing of other components. However, when running in PlanAhead, other component's elements are being placed in this range. Does PlanAhead ignore my constraint?
举报
