LTspice和geneys线性模拟之间的差异

我不知道这是不是正确的解释，但我会试一试。
我自己已经在几个pkgs中模拟了这一点，包括geneys，ansys设计师，TINA（TI的spice程序）和LT spice。
是的，我对此感到好奇，因为它让我感到烦恼。
对于你的电路，一个反相运算放大器，如果你忽略了分流电容，你的总增益为1000/50 = 20，就dB而言，大约为26dB。
如果你将100欧姆负载分成两个50欧姆，你会得到另外6dB的损失。
Genesys给你26dB，但LTspice说20dB。
我相信这是因为使用LTspice可以直接访问Vin和Vout的节点电压，并且可以通过这种方式进行数学运算。
与geneys没那么多。
我的geneys版本只有线性分析。
我想如果你有时间域或HB pkgs那么也许你可以这样做。
我认为这是因为在Ansys（又名Ansoft）中我可以设置类似于LTspice / genesys的模拟，我也可以获得节点电压。
当我使用RF端口运行sim时，我得到的就像你在geneys中看到的一样。
当我使用离散交流电源运行电路并在输入和输出端使用电压探头时，我可以获得LTspice为您提供的等效图。
所以我现在的想法是，由于geneys在进行线性分析时无法访问电压节点，因此您可以自行了解这一方面。
如果我无法访问这么多工具，我会摸不着头脑。
我总是建议使用多个工具来验证可能的时间。
丹尼斯



     以下为原文

  I don't know if this is the correct explanation but I am going to give this a shot.  I myself have simulated this in several pkgs including genesys, ansys designer, TINA (TI's spice program) and LT spice.  And yes, I was curious about this because it bugged me.

For your circuit, an inverting op amp, if you ignore the shunt cap for the moment you have an overall gain of 1000/50 = 20, in terms of dB this is about 26dB.  If you throw in the 100ohm load divided into two 50ohms, you get another 6dB of loss.  Genesys gives you 26dB but LTspice is saying 20dB.  I believe this is because with LTspice you have access the the nodal voltages of Vin and Vout directly and can do the math that way.  With genesys not so much.  My genesys version only has linear analysis.  I suppose if you have the time domain or HB pkgs then maybe you could do it that way.  I figured this out because in Ansys (aka Ansoft) I can setup a simulation similarly to both LTspice/genesys and I can get access to nodal voltages too.  When I run the sim with RF ports I get the same as you are seeing in genesys.  When I run the circuit with a discrete ac source and use voltage probes at the input and output, I can get the equivalent plot that LTspice gives you.   So my thoughts right now are that since genesys does not give access to voltage nodes while doing linear analysis then it would be up to you to know that aspect.  If I did not have access to so many tools I would be scratching my head.  I would always suggest using more than one tool to verify when possible.   

dennis

嗨，我使用ADS来比较设计，因为ADS可以模拟AC和S_Parameter模拟。
在AC模拟器中运行模拟，LTSpice大约为20dB。
在S_Parameter仿真中运行相同的电路，得到26dB作为Genesys。
由于SPICE仿真器不能模拟S参数，我们必须从复杂的电压和电流计算它们。
S21 = 2 * Vout / Vin该因子2适用于AC和S-par数据之间的6 dB差异。
我也模拟了Genesys中的电路并且确实得到了过冲（如在ADS / LTSpice中）我认为SPICE导入连接p1和p2（IN-和IN +）被交换...在导入期间你得到的问题，我
将此保留为默认值，即为所有设备交换端口1和端口2。
参考。
建模手册章节 - 如何从SPICE获取S参数曲线http://edadocs.software.keysight.com/display/iccapmhb/S+Parameter+Curves+form+SPICE ReintEdited by：relange on Jan 6,2015 6
：晚上28点



     以下为原文

  Hi,

I used ADS to compare the designs, because ADS can simulate AC and S_Parameter simulations.

Running the simulation in AC simulator gives as LTSpice about 20dB.
Running the same circuit in S_Parameter simulation gives 26dB as Genesys.

Since SPICE simulator cannot simulate S-parameter, we have to calculate them from the complex voltages and currents.
S21 = 2 * Vout / Vin  
This factor of 2 is good for the 6 dB difference between AC and S-par data.

I simulated the circuit in Genesys as well and do get the overshoot (as in ADS/LTSpice)
I think that the SPICE import the connection p1 and p2 (IN- and IN+) are exchanged...
During import you get the question, I kept this at default, which is exchange PORT 1 and PORT 2 for all devices.



Ref.  Chapter from Modeling Handbook -- How to Obtain S-Parameter Curves from SPICE

http://edadocs.software.keysight.com/display/iccapmhb/S+Parameter+Curves+form+SPICE

Reint

Edited by: relange on Jan 6, 2015 6:28 PM