包装错误2908是关于什么的？

消除过程的好抓！
看起来
IOSTANDARD = LVDS_25;
// *不好。
IOSTANDARD = LVDS25;
// 好
如果PlanAhead生成了错误的.UCF文件语法，则表示您应该报告的错误（请打开Webcase）。
目前尚不清楚该错误是出现在PlanAhead中是为了生成错误的语法，还是在ISE中的某个其他地方出现不一致的约束形式处理，或两者兼而有之。
如果您错误地手动指定了IOSTANDARD，那么问题就解决了。
在任何一种情况下，请将此主题标记为“已解决”，并接受我们的谢意，以便发现并记录它。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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在原帖中查看解决方案



以下为原文

Good catch by process of elimination!
 
It seems that
IOSTANDARD = LVDS_25;  // *NOT* OK.
IOSTANDARD = LVDS25;   // OK
 
If PlanAhead generated the incorrect .UCF file syntax, this represents a bug that you should report (by opening a webcase, please).  It's not clear whether the bug is in PlanAhead for generating incorrect syntax, or somewhere else in ISE for inconsistent handling of a constraint form, or both.
 
If you manually specified the IOSTANDARD incorrectly, then your problem is solved.
 
In either case, please mark this thread as "SOLVED", and accept our thanks for uncovering and documenting it.
 
- Bob Elkind
SIGNATURE:
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Summary:
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是13.1 64位



以下为原文

ise 13.1 64 bit

错误是I / O组件“io_p”具有非法的IOSTANARD值LVDS_25。
我看vhd缓冲区的ibfudsgeneric地图（iostandard =>“LVDS_25”，IFD_DELAY_VALUE =>“0”，DIFF_TERM => TRUE）



以下为原文

the error is I/O component "io_p" has illegal IOSTANARD value LVDS_25.  i look the vhd buffer its  

ibfuds
generic map(
iostandard => "LVDS_25",
IFD_DELAY_VALUE => "0",
DIFF_TERM => TRUE)

错误是I / O组件“io_p”具有非法的IOSTANARD值LVDS_25
在同一个IO银行中使用了哪些其他IOSTANDARD？
该信号所在的IO bank的VCCO是什么？
这个信号是差分对的一半吗？
LVDS用于差分信号，而不是单端信号。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

the error is I/O component "io_p" has illegal IOSTANARD value LVDS_25
 
what other IOSTANDARDs are in use in the same IO bank?
What is VCCO for the IO bank in which this signal is located?
Is this signal half of a diff pair?  LVDS is for differential signals, not single-ended signals.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.