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[问答]

在Coolrunner2系列CPLD上实现一个系统但删除了有用的输入

你好,
我正在尝试在Coolrunner2系列CPLD上实现一个系统。
该系统通过不同的输入进行控制。
其中一个编码为2个字节,在翻译期间被删除。
[警告]:Cpld:1007  - 删除未使用的输入'my_input'。

优化后输入未使用。
请通过验证功能
模拟。
[警告]:Cpld:1007  - 删除未使用的输入'my_input'。

优化后输入未使用。
请通过验证功能
模拟。
行为模拟显示此输入是必需的。
如果删除它,大多数输出​​都不会改变。
我无法运行拟合后模拟,因为Modelsim要求删除输入:
#**警告:[1] rotativ_bench.vhd(47):没有组件'rotative_box'的默认绑定。
(端口'my_input'不在实体上。)
更令人奇怪的是,我在一个进程的敏感列表中使用此输入。
此外,如果我尝试约束.UCF文件中“my_input”的位置,则转换不会完成:
错误:NgdBuild:755  - 'rotativ_const.ucf'中的第1行:找不到网络
错误:NgdBuild:755  - 'rotativ_const.ucf'中的第2行:找不到网络
如果有人有想法,任何帮助都会受到赞赏。
谢谢。

以上来自于谷歌翻译


以下为原文

Hello,

I am trying to implement a system on a Coolrunner2 family CPLD. This system is controled through different inputs. One of them, coded on 2 bytes, is removed during the translation.
[Warning]:Cpld:1007 - Removing unused input(s) 'my_input<0>'. The input(s) are unused after optimization. Please verify functionality via simulation.
[Warning]:Cpld:1007 - Removing unused input(s) 'my_input<1>'. The input(s) are unused after optimization. Please verify functionality via simulation.

The behavioral simulation shows that this input is required. If it is removed, most of the ouputs do not change.
I could not run post-fit simulation, because Modelsim asked for the removed input :

# ** Warning: [1] rotativ_bench.vhd(47): No default binding for component 'rotative_box'. (Port 'my_input' is not on the entity.)

It is even more strange that I use this input in the sensitive list of a process.
Moreover, if i try to constraint location for 'my_input' in a .UCF file, the translation does not complete :

ERROR:NgdBuild:755 - Line 1 in 'rotativ_const.ucf': Could not find net(s)
ERROR:NgdBuild:755 - Line 2 in 'rotativ_const.ucf': Could not find net(s)

If someone has an idea, any help would be apprecitated. Thanks.

回帖(3)

杨玲

2018-10-8 17:56:11
修整消息指的是两位,而不是两个字节。
确保你真的使用了
输入字中的两个引用位。
-  Gabor

以上来自于谷歌翻译


以下为原文

The trimming message is referring to two bits, not two bytes.  Make sure you actually use the
two referenced bits in the input word.
-- Gabor
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高若琰

2018-10-8 18:02:32
这两位被称为输入。
在合成中似乎没有问题。
RTL原理图显示这些位被识别为输入。
请。
我该怎么办 ?

以上来自于谷歌翻译


以下为原文

The two bits are referenced as inputs.
It seems there is no problem durins the synthesis. And the RTL schematic shows that the bits are recognized as inputs.
Please. What should i do ?
举报

黄淳

2018-10-8 18:13:28
None
以上来自于谷歌翻译


以下为原文

thefoxof33 wrote:
The two bits are referenced as inputs.
It seems there is no problem durins the synthesis. And the RTL schematic shows that the bits are recognized as inputs.
Please. What should i do ?
The two bits may be "referenced as inputs" but the logic may actually not need those two bits, and as such the tools remove them.
 
Check your code again.
 
You get the UCF failures because the tools removed those inputs.
 
-a
----------------------------Yes, I do this for a living.
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