嗨,Rajath,
我分享的原理图是最初的版本,我稍微修改了原理图。我已经添加了一个与MOSFET栅极和CGG2引脚21和24串联的68 K电阻,之后,cc1和cc2引脚开始切换到40ms。
我问的5V电流要求的原因是使用LDO代替开关稳压器。在当前的电路图(主项目)中,我们有一个开关稳压器,它提供高达6A的电流,并且已经连接到双P通道,但是当我们没有从开关稳压器中汲取电流时,工作电流将比操作电流O高一点。F LDO。为了减少理想模式下由系统引起的输入电流,我们正计划使用LDO来驱动双P沟道MOSFET,并且在理想模式下系统关闭开关稳压器。
我们在不断地测试董事会,而CGG没有停止工作。一旦年停止工作我将检查你所用示波器的点和分享你的照片。
谢谢,
纳加拉杰
以上来自于百度翻译
以下为原文
Hi Rajath,
The schematics which I shared is the initial release and I have slightly modified the schematics. I have added a 68K resistor in series with MOSFET gate and CCG2 pins 21 and 24, after which the CC1 and CC2 pins started toggling at ~40ms.
The reason why I asked about the 5V current requirement was to use a LDO instead of switching regulator. In the current schematics (The main project) we have a switching regulator which will provide up to 6A of current and the same has been connected to dual P channel, but when we are not drawing the current from switching regulator the operating current will be bit higher than the operating current of LDO. To reduce the input current drawn by the system in Ideal mode we are planning to use LDO to power dual p channel mosfet and switch off the switching regulator when the system in ideal mode.
We are continuously testing the board and the CCG didn't stop working. Once the CCCG stops working I will check the points you mentioned using oscilloscope and share you the pic.
Thanks,
Nagaraj
嗨,Rajath,
我分享的原理图是最初的版本,我稍微修改了原理图。我已经添加了一个与MOSFET栅极和CGG2引脚21和24串联的68 K电阻,之后,cc1和cc2引脚开始切换到40ms。
我问的5V电流要求的原因是使用LDO代替开关稳压器。在当前的电路图(主项目)中,我们有一个开关稳压器,它提供高达6A的电流,并且已经连接到双P通道,但是当我们没有从开关稳压器中汲取电流时,工作电流将比操作电流O高一点。F LDO。为了减少理想模式下由系统引起的输入电流,我们正计划使用LDO来驱动双P沟道MOSFET,并且在理想模式下系统关闭开关稳压器。
我们在不断地测试董事会,而CGG没有停止工作。一旦年停止工作我将检查你所用示波器的点和分享你的照片。
谢谢,
纳加拉杰
以上来自于百度翻译
以下为原文
Hi Rajath,
The schematics which I shared is the initial release and I have slightly modified the schematics. I have added a 68K resistor in series with MOSFET gate and CCG2 pins 21 and 24, after which the CC1 and CC2 pins started toggling at ~40ms.
The reason why I asked about the 5V current requirement was to use a LDO instead of switching regulator. In the current schematics (The main project) we have a switching regulator which will provide up to 6A of current and the same has been connected to dual P channel, but when we are not drawing the current from switching regulator the operating current will be bit higher than the operating current of LDO. To reduce the input current drawn by the system in Ideal mode we are planning to use LDO to power dual p channel mosfet and switch off the switching regulator when the system in ideal mode.
We are continuously testing the board and the CCG didn't stop working. Once the CCCG stops working I will check the points you mentioned using oscilloscope and share you the pic.
Thanks,
Nagaraj
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