【原创】基于 FPGA音频分析仪
介绍之前先说说图形驱动：
送一张基德给大家^^
—12864图形显示驱动是由Verilog编写，经常硬件编程的同学都知道，硬件描述语言并行语句的特性，使得原本C语言或者单片
机相对容易描述的逻辑变得很蛋疼。。。==！
这时就需要状态机了，状态机的描述就显得尤为重要。
也许我见识浅短，还没有发现用Verilog或者VHDL编写的12864图形驱动。所以下决心写一个。走了很多弯路还是搞定了。
对了，大家一定要注意Verilog中“阻塞赋值语句”和“非阻塞赋值语句”的区别！经常便便。。。==。打错了。。经常编编程序就
理解了，很重要。
四个柱状条显示声音实时变化的幅度。音频信号由麦克风采集进来，经过WM8731处理音频信息，放出16bit声音信号，再送
FPGA处理显示，视频里大家可以看得很清楚。
技术的路上大家交流，我不爱dota，喜欢设计一样也能快乐得废寝忘食。
大家加油！
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不错。。。。。。。。。。。。。。。。。。。。。。。。。。。
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楼主很有想法 
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以下是图形显示的驱动部分代码，大家可以看看。
//32 state machines
parameter s1 = 6'b000000;
parameter s2 = 6'b000001;
parameter s3 = 6'b000010;
parameter s4 = 6'b000011;
parameter s5 = 6'b000100;
parameter s6 = 6'b000101;
parameter s7 = 6'b000110;
parameter s8 = 6'b000111;
parameter s9 = 6'b001000;
parameter s10 = 6'b001001;
parameter s11 = 6'b001010;
parameter s12 = 6'b001011;
parameter s13 = 6'b001100;
parameter s14 = 6'b001101;
parameter s15 = 6'b001110;
parameter s16 = 6'b001111;
parameter s17 = 6'b010000;
parameter s18 = 6'b010001;
parameter s19 = 6'b010010;
parameter s20 = 6'b010011;
parameter s21 = 6'b010100;
parameter s22 = 6'b010101;
parameter s23 = 6'b010110;
parameter s24 = 6'b010111;
parameter s25 = 6'b011000;
parameter s26 = 6'b011001;
parameter s27 = 6'b011010;
parameter s28 = 6'b011011;
parameter s29 = 6'b011100;
parameter s30 = 6'b011101;
parameter s31 = 6'b011110;
parameter s32 = 6'b011111;
parameter s33 = 6'b100001;
parameter s34 = 6'b100010;
parameter s35 = 6'b100011;
reg [5:0] state; //State Machine code
reg [10:0] char_cnt;
reg [10:0] clear_cnt;
reg [7:0] data_disp;
reg [7:0] RAM_Y;
reg [7:0] RAM_X;
// State Machine
always @(posedge CLK_LCD or negedge RST_N)
begin
if(!RST_N)
begin
state <= s1;
end
else
begin
case(state)
s1:
begin
state <=s2;
char_cnt <= 11'b0;
clear_cnt<= 11'b0;
RAM_Y =8'h80;
RAM_X =8'h80;
LCD_RS <=1'b0;//LCD_RS <=High is write command
LCD_RW <=1'b0;
LCD_D <=8'h30;
LCD_E <=1'b1;
end
s2:
begin
state <=s3;
LCD_E <=1'b0;
end
s3:
begin
state <=s4;
LCD_D <=8'h0C;
LCD_E <=1'b1;
end
s4:
begin
state <=s5;
LCD_E <=1'b0;
end
s5:
begin
state <= s6;
LCD_D <=8'h01;
LCD_E <=1'b1;
end
s6:
begin
state <=s7;
LCD_E <=1'b0;
end
s7:
begin
state <=s8;
LCD_RS <=1'b0;
LCD_D <=8'h34;
LCD_E <=1'b1;
end
s8:
begin
state <=s9;
LCD_E <=1'b0;
end
s9:
begin
state <=s10;
LCD_RS <=1'b0;
LCD_D <=8'h34;
LCD_E <=1'b1;
end
s10:
begin
state <=s11;
LCD_E <=1'b0;
end
s11:
begin
state <=s12;///////////////
LCD_RS <=1'b0;
LCD_E <=1'b1;
case(clear_cnt)
//Up screen
0:
RAM_Y =8'h80;
16:
RAM_Y =8'h81;
32:
RAM_Y =8'h82;
48:
RAM_Y =8'h83;
64:
RAM_Y =8'h84;
80:
RAM_Y =8'h85;
96:
RAM_Y =8'h86;
112:
RAM_Y =8'h87;
128:
RAM_Y =8'h88;
144:
RAM_Y =8'h89;
160:
RAM_Y =8'h8A;
176:
RAM_Y =8'h8B;
192:
RAM_Y =8'h8C;
208:
RAM_Y =8'h8D;
224:
RAM_Y =8'h8E;
240:
RAM_Y =8'h8F;
256:
RAM_Y =8'h90;
272:
RAM_Y =8'h91;
288:
RAM_Y =8'h92;
304:
RAM_Y =8'h93;
320:
RAM_Y =8'h94;
336:
RAM_Y =8'h95;
352:
RAM_Y =8'h96;
368:
RAM_Y =8'h97;
384:
RAM_Y =8'h98;
400:
RAM_Y =8'h99;
416:
RAM_Y =8'h9A;
432:
RAM_Y =8'h9B;
448:
RAM_Y =8'h9C;
464:
RAM_Y =8'h9D;
480:
RAM_Y =8'h9E;
496:
RAM_Y =8'h9F;
512:
RAM_Y =8'h80;
528:
RAM_Y =8'h81;
544:
RAM_Y =8'h82;
560:
RAM_Y =8'h83;
576:
RAM_Y =8'h84;
592:
RAM_Y =8'h85;
608:
RAM_Y =8'h86;
624:
RAM_Y =8'h87;
640:
RAM_Y =8'h88;
656:
RAM_Y =8'h89;
672:
RAM_Y =8'h8A;
688:
RAM_Y =8'h8B;
704:
RAM_Y =8'h8C;
720:
RAM_Y =8'h8D;
736:
RAM_Y =8'h8E;
752:
RAM_Y =8'h8F;
768:
RAM_Y =8'h90;
784:
RAM_Y =8'h91;
800:
RAM_Y =8'h92;
816:
RAM_Y =8'h93;
832:
RAM_Y =8'h94;
848:
RAM_Y =8'h95;
864:
RAM_Y =8'h96;
880:
RAM_Y =8'h97;
896:
RAM_Y =8'h98;
912:
RAM_Y =8'h99;
928:
RAM_Y =8'h9A;
944:
RAM_Y =8'h9B;
960:
RAM_Y =8'h9C;
976:
RAM_Y =8'h9D;
992:
RAM_Y =8'h9E;
1008:
RAM_Y =8'h9F;
default:RAM_Y =RAM_Y;
endcase
LCD_D = RAM_Y;
end
s12:
begin
state <=s13;
LCD_E <=1'b0;
end
s13:
begin
state <=s14;
LCD_E <=1'b1;
if( clear_cnt<512)
if(clear_cnt==0)
RAM_X =8'h80;
else
if( RAM_X==8'h87)
RAM_X =8'h80;
else
RAM_X =RAM_X+1'b1;
else
if(clear_cnt==512)
RAM_X =8'h88;
else
if( RAM_X==8'h8F)
RAM_X =8'h88;
else
RAM_X =RAM_X+1'b1;
LCD_D = RAM_X;
end
s14:
begin
state <=s15;
LCD_E <=1'b0;
end
s15:
begin
state <=s16;
LCD_RS <=1'b1;//LCD_RS <= Low is write data
LCD_D <=8'h00;//High-8bits
LCD_E <=1'b1;
end
s16:
begin
state <=s17;
LCD_E <=1'b0;
end
s17:
begin
state <=s18;
LCD_RS <=1'b1;
LCD_D <=8'h00;//Low_8bits
LCD_E <=1'b1;
end
s18:
begin
state <=s19;
LCD_E <=1'b0;
end
s19:
begin
if(clear_cnt==1024)
begin
state <=s20;//LCD_RS<=1'b1 before!!!
LCD_RS <=1'b0;
clear_cnt<=0;
end
else
begin
clear_cnt<=clear_cnt + 2;
LCD_RS <=1'b0;
state <=s7;//>>>>>>>>>>
end
end
s20:
begin
state <=s21;
LCD_D <=8'h34;
LCD_E <=1'b1;
end
s21:
begin
state <=s22;
LCD_E <=1'b0;
end
s22:
begin
state <=s23;
LCD_RS <=1'b0;//write command
LCD_D <=8'h34;
LCD_E <=1'b1;/////
end //
s23:
begin //
state <=s24; //
LCD_E <=1'b0; /////
end
s24:
begin
state <=s25;
LCD_RS <=1'b0;
LCD_E <=1'b1;
case(char_cnt)
//Up screen
0:
RAM_Y =8'h80;
16:
RAM_Y =8'h81;
32:
RAM_Y =8'h82;
48:
RAM_Y =8'h83;
64:
RAM_Y =8'h84;
80:
RAM_Y =8'h85;
96:
RAM_Y =8'h86;
112:
RAM_Y =8'h87;
128:
RAM_Y =8'h88;
144:
RAM_Y =8'h89;
160:
RAM_Y =8'h8A;
176:
RAM_Y =8'h8B;
192:
RAM_Y =8'h8C;
208:
RAM_Y =8'h8D;
224:
RAM_Y =8'h8E;
240:
RAM_Y =8'h8F;
256:
RAM_Y =8'h90;
272:
RAM_Y =8'h91;
288:
RAM_Y =8'h92;
304:
RAM_Y =8'h93;
320:
RAM_Y =8'h94;
336:
RAM_Y =8'h95;
352:
RAM_Y =8'h96;
368:
RAM_Y =8'h97;
384:
RAM_Y =8'h98;
400:
RAM_Y =8'h99;
416:
RAM_Y =8'h9A;
432:
RAM_Y =8'h9B;
448:
RAM_Y =8'h9C;
464:
RAM_Y =8'h9D;
480:
RAM_Y =8'h9E;
496:
RAM_Y =8'h9F;
512:
RAM_Y =8'h80;
528:
RAM_Y =8'h81;
544:
RAM_Y =8'h82;
560:
RAM_Y =8'h83;
576:
RAM_Y =8'h84;
592:
RAM_Y =8'h85;
608:
RAM_Y =8'h86;
624:
RAM_Y =8'h87;
640:
RAM_Y =8'h88;
656:
RAM_Y =8'h89;
672:
RAM_Y =8'h8A;
688:
RAM_Y =8'h8B;
704:
RAM_Y =8'h8C;
720:
RAM_Y =8'h8D;
736:
RAM_Y =8'h8E;
752:
RAM_Y =8'h8F;
768:
RAM_Y =8'h90;
784:
RAM_Y =8'h91;
800:
RAM_Y =8'h92;
816:
RAM_Y =8'h93;
832:
RAM_Y =8'h94;
848:
RAM_Y =8'h95;
864:
RAM_Y =8'h96;
880:
RAM_Y =8'h97;
896:
RAM_Y =8'h98;
912:
RAM_Y =8'h99;
928:
RAM_Y =8'h9A;
944:
RAM_Y =8'h9B;
960:
RAM_Y =8'h9C;
976:
RAM_Y =8'h9D;
992:
RAM_Y =8'h9E;
1008:
RAM_Y =8'h9F;
default:RAM_Y =RAM_Y;
endcase
LCD_D = RAM_Y;
end
s25:
begin
state <=s26;
LCD_E <=1'b0;
end
s26:
begin
state <=s27;
LCD_RS <=1'b0;
LCD_E <=1'b1;
if( char_cnt<512)
if(char_cnt==0)
RAM_X=8'h80;
else
if( RAM_X==8'h87)
RAM_X=8'h80;
else
RAM_X=RAM_X+1'b1;
else
if(char_cnt==512)
RAM_X =8'h88;
else
if( RAM_X==8'h8F)
RAM_X =8'h88;
else
RAM_X=RAM_X+1'b1;
LCD_D = RAM_X;
end
s27:
begin
state <=s28;
LCD_E <=1'b0;
end
s28:
begin
state <=s29;
LCD_RS <=1'b0;//write command
end
s29:
begin
if(char_cnt==1024)
begin
state <= s30;//>>>>>>>>>>>>>>>>>>>>>>>>>>>>
char_cnt<=0;
LCD_D <= 8'h36;
LCD_E <=1'b1;
end
else
begin
state <= s31;
LCD_RS <=1'b1;//write data
LCD_E <=1'b1;
end
end
s30:
begin
state <= s24;//no change
LCD_E <=1'b0;
end
s31:
begin
state <= s32;
LCD_RS <=1'b1;
LCD_D <= data_disp;//high 8bits
char_cnt<= char_cnt + 1'b1;
end
s32:
begin
state <= s33;
LCD_E <=1'b0;//>>>>>>>>>>>>>>>>>>>>>>>>
end
s33:
begin
state <= s34;
LCD_RS <=1'b1;
LCD_D <= data_disp;//low 8bits
LCD_E <=1'b1;
char_cnt<= char_cnt + 1'b1;
end
s34:
begin
state <= s35;
LCD_E <=1'b0;
end
s35:
state <= s24;//>>>>>>>>>>>>>>>>>>>>>>>>
default:state <= s1;
endcase
end
end
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紫风幻月 发表于 2013-5-31 20:50 ![]()
楼主可有Verilog代码 或者思路，流程图什么的？ 12864显示图片不知怎么控制 ...
图形显示部分代码已经共享。
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944456214 发表于 2013-6-9 11:52 ![]()
你好！我也很喜欢FPGA，可不可以将你写的代码发一份给我啊！邮箱：
图形显示部分代码已经共享。
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楼主真厉害 
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对于图像驱动，有一些什么；类型的书籍推荐的，自己由单片机与fpga结合采用spi
通信的
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能人，高手，大神啊
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求程序，求指导，高了好长时间就是不出结果。还有像问一句是不是用nios搞的啊？
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