FPGA设计高级技巧Xilinx篇

FPGA设计高级技巧Xilinx篇.rar

FPGA设计高级技巧Xilinx篇.rar (1.63 MB, 下载次数: 713 )

FPGA设计高级技巧Xilinx篇

目录
41
4.3 减少关键路径的逻辑级数
.............................................
40
4.2IF语句和Case语句速度与面积的关系...................................
39
4.1.2 使用圆括号处理多个加法器
.......................................
38
4.1.1 串行进位与超前进位............................................
38
4.1 合理选择加法电路
..................................................
37
4 设计技巧..............................................................
35
3.8.2 解剖Block SelectRAM内部结构
....................................
34
3.8.1 LUT如何配置成组合逻辑电路揭开门数增加逻辑级数未
变但资源占用减少速度更快之谜..................................
33
3.8 补充说明..........................................................
32
3.7.3 DCM
........................................................
30
3.7.2 CLK MUX....................................................
29
3.7.1 Global Clock
...................................................
29
3.7 Clock Resource
.....................................................
29
3.6.3 DCI
.........................................................
28
3.6.2 Select I/O
.....................................................
27
3.6.1 IOB结构
......................................................
27
3.6 IOB
..............................................................
25
3.5 乘法器资源
........................................................
23 3.4.2 Block RAM
...................................................
21
3.4.1 Distributed RAM
................................................
21
3.4 Memory
...........................................................
21
3.3.8 FFX/FFY
.....................................................
20
3.3.7 SOP
.........................................................
17
3.3.6 Carry Logic 和Arithmetic Logic Gates
................................
16
3.3.5 MUXFX......................................................
16
3.3.4 Shift Register LUT SRL
.......................................
15
3.3.3 LUT
.........................................................
14
3.3.2 Slice
........................................................
13
3.3.1 CLB
.........................................................
12
3.3 结构概述
..........................................................
12
3.2 VirtexII功能概述....................................................
11
3.1.3 Coding Style的对比
.............................................
11
3.1.2 ASIC结构.....................................................
11
3.1.1 FPGA结构
....................................................
11
3.1 器件结构对Coding Style的影响.........................................
10
3 FPGA器件结构 VirtexII
................................................
10
2.3 综合性能对Coding Style 影响..........................................
10
2.2 不同综合工具的性能
.................................................
9
2.1 理解综合两个过程 ...................................................
8
2 综合工具与代码风格
......................................................
8
1 前言...................................................................