数码管小程序有小问题，哪位大神帮帮我这个新手

ti

本帖最后由 eehome 于 2013-1-5 09:44 编辑

module Tube(
  CLK,
  RST_N,
  DATA,
  SEL
  );
input CLK;
input RST_N;
output [7:0]DATA;
output [7:0]SEL;          //数码管公共端
reg [7:0]DATA_R;
reg [23:0]tiME_CNT;
reg [3:0]NUM;
//------------------------------------------------------
//计时 TIME_CNT
always @( posedge CLK or negedge RST_N) begin
if(!RST_N) TIME_CNT <= 24'B0;
else TIME_CNT <= TIME_CNT + 1'B1;
end
//-------------------------------------------------------------
//每2的24次方时钟周期，数字+1
always @( posedge CLK or negedge RST_N) begin
if(!RST_N) NUM <= 4'h0;
else if(TIME_CNT == 24'hFF_FFFF)  NUM <= (NUM == 9)? 4'H0 : NUM + 4'B1;
end
//----------------------------------------------------------
parameter num_0 = 8'b1100_0000,
num_1 = 8'b1111_1001,
num_2 = 8'b1010_0100,
num_3 = 8'b1011_0000,
num_4 = 8'b1001_1001,
num_5 = 8'b1001_0010,
num_6 = 8'b1000_0010,
num_7 = 8'b1111_1000,
num_8 = 8'b1000_0000,
num_9 = 8'b1001_0000;
//------------------------------------------------------------------
always @(NUM)begin
case(NUM)
0 : DATA_R = num_0;
1 : DATA_R = num_1;
2 : DATA_R = num_2;
3 : DATA_R = num_3;
4 : DATA_R = num_4;
5 : DATA_R = num_5;
6 : DATA_R = num_6;
7 : DATA_R = num_7;
8 : DATA_R = num_8;
9 : DATA_R = num_9;
default : ;
endcase
end
//---------------------------------------------------------------------
assign DATA = DATA_R;
assign SEL = 8'b1111_0001;
endmodule

仿真成功，下载到板上也没问题。但有个警告
Warning (10240): Verilog HDL Always Construct warning at Tube.v(46): inferring latch(es) for variable "DATA_R", which holds its previous value in one or more paths through the always construct
Warning: Latch DATA_R[0] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal NUM[1]...............................

想知道怎样才没有这警告。。。。

文扬 · 2013-12-5 22:45:58

多周期保持,差不多就是生成了锁存器

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数码管小程序有小问题，哪位大神帮帮我这个新手

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