电子时钟VHDL程序与仿真

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times New="New" Roman'; mso-bidi-font-family: 'Times New="New" Roman'; mso-ascii-font-family: 'Times New="New" Roman'; mso-ansi-language: EN-US; mso-fareast-language: ZH-CN; mso-bidi-language: AR-SA">电子时钟VHDL程序与仿真

1. 10进制计数器设计与仿真
（1）10进制计数器VHDL程序
--文件名：counter10.vhd。
--功能：10进制计数器，有进位C
--最后修改日期：2004.3.20
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter10 is
    Port ( clk : in std_logic;
          reset : in std_logic;
          din : in std_logic_vector(3 downto 0);
          dout : out std_logic_vector(3 downto 0);
    c:out std_logic);
end counter10;
architecture Behavioral of counter10 is
   signal count : std_logic_vector(3 downto 0);
begin
    dout <= count;
 process(clk,reset,din)
 begin
    if reset='0'then
   count <= din ;
   c<='0';
       elsif rising_edge(clk) then
     if count = "1001" then
      count <= "0000";
      c<='1';
           else
      count <= count+1;
      c<='0';
           end if;
      end if;
    end process;
end Behavioral;
（2） 10进制计数器仿真

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