降压功率级设计公式

摘要：本应用笔记解释了如何通过选择合适的外部元件来实现为其他模块供电的降压电压，从而构建集成降压转换器功率级。

介绍

当系统具有高功率要求时，开关稳压器始终是首选。它们提供高效率和紧凑的 PCB 解决方案尺寸，以实现令人满意的电源。本应用笔记提供的方程式有助于在实现定制电压时选择降压型开关稳压器所需的外部元件。

降压转换器配置

作为图1所示的基本降压开关稳压器配置，当高边开关在时钟开关周期开始时导通时，低边开关同时关断。V断续器等于电源电压 V 在 ;当高边开关关闭时，低边开关在时钟开关周期的静止时间间隔内导通，并且V断续器等于接地电压，忽略开关电流 I 引入的高端和低端功率FET 上的压降房 协和我断续器分别流经环路。出现在V上的方波信号断续器通过LC滤波器，产生恒定输出电压V 外 ，由 V 的占空比 D 控制 断续器 .

同时，在高边开关导通时间间隔期间，电感电流I断续器斜坡上升以存储电感器的能量，并且与低侧开关ON时间间隔相反，I断续器斜坡下降以释放电感器内部存储的能量。电感电流I的平均值断续器维持开关稳压器供电的直流负载，电感纹波电流流入输出电容，通过电容和输出电容等效串联电阻（ESR）产生输出电压纹波。

图 1.降压转换器配置

图 2.降压转换器波形

选择电感器

在连续导通模式下，电源开关在开关周期内的每个状态下消耗功率损耗。增加的电感电流仍然等于降低的电感电流。占空比按以下公式排列：

等式 （1）

其中参数为：V 外 ： 稳压输出电压V 在 ： 电源输入电压V 电除尘器 ： HS 开关V 两端的压降 断续器 ： LS开关两端的压降 忽略V时，占空比仅由输入电压和输出电压决定电除尘器和 V 断续器 :

等式 （2）

电感值越高，产生的电流纹波越小，ΔI断续器和峰值电流值 I 峰 ，这决定了开关稳压器IC输出的最大负载电流，也感应出较小的输出电压纹波。我峰应小于IC可以提供的ILIM的最小值。

开关稳压器IC数据手册提供了电感选择范围，通常为固定的标称值\pm容差%，并且器件内部斜率补偿针对在可接受范围内选择的外部电感值进行了优化。一旦选择了电感值，峰值电流就导出为直流输出负载加一半的电感纹波电流。

电感纹波电流和峰值电流表示为：

等式 （3）

Equation (4)

where the parameters are:V OUT : Regulated output voltageV IN : Supply input voltageD: Duty cycle derived from Equation (2)f sw : Switching frequency on systemL: Inductor valueI LOAD : Load current required from ICThe RMS current flowing through the inductor is:

Equation 5

where the parameters are:I LOAD : Load current required from ICΔI LX : Inductor ripple current value from Equation (3)

Select inductors having a higher root mean square (RMS) current rating to avoid overheating impacting the efficiency and performance. The saturation current of the inductor stated in the data sheet should be larger than the maximum value of IPEAK in a given range of VIN so that the inductance value does not drop too much by a certain number. A smaller inductor value has low cost and saves PCB area, but has larger current ripple, conducting more AC core power loss dissipated on it, combining with the conduction power loss from the DCR value of the inductor. The significant power dissipated on the inductor also heats up the whole compact solution area, lowering efficiency, especially for heavy output load current.

Selecting the Input Capacitor

When the high-side switch is in the ON state, the switching current flowing on the IC input path carries switching noise, and the input capacitor filters out most noise effectively and reduces input voltage ripple. The larger the load current drawn from the output, the larger the voltage ripple that is seen on the input. Place the input ceramic capacitor as close to the switching regulator as possible.

Calculate the input capacitance for a specified input voltage ripple as:

Equation (6)

where the parameters are:I LOAD : Load current required from ICD: Duty cycle derived from Equation (2)f sw : Switching frequency on systemΔV IN : Input voltage ripple requirementThe input voltage ripple contribution from the ESR is expressed as:

Equation (7)

where the parameters are:I LOAD : Load current required from ICΔI LX : Inductor ripple current value from Equation (3)R ESR : Equivalent series resistance of output capacitors networkThe input capacitor RMS current is expressed as:

Equation (8)

where the parameters are:V OUT : Regulated output voltageV IN : Supply input voltageI LOAD : Load current required from IC

The ICIN(RMS) value should be less than the RMS rating of capacitors stated in the data sheet. Use low ESR ceramic capacitors to minimize the supply voltage ripple when large current ripple is flowing through input so that the X7R dielectric material has better temperature characteristics to handle less capacitance change with temperature rise on capacitors.

The actual ceramic capacitance should be larger than the value calculated above to give some margin on the capacitance loss by DC bias voltage derating. Follow the data sheet component selection guide for minimum ceramic capacitance needed to stabilize the input voltage. One 0.1µF ceramic capacitor should be preferably placed in parallel, decoupling high frequency noise on the input. Add aluminum bulk capacitance to provide large current during load transient and maintain an allowable input voltage deviation.

Selecting the Output Capacitor

The output voltage ripple is contributed by the capacitor elements capacitance and ESR in steady state. Use low ESR, X7R ceramic capacitors to minimize the output voltage ripple.

The output capacitance with a specific output voltage ripple requirement is expressed as:

Equation (9)

where the parameters are:ΔI LX : Inductor ripple current calculated value from Equation (3)f sw : Switching frequency on systemΔV OUT : Output voltage ripple requirementThe output voltage ripple contribution from ESR is expressed as:

Equation (10)

where the parameters are:ΔI LX : Inductor ripple current calculated value from Equation (3)R ESR : Equivalent series resistance of output capacitors network

The capacitance is usually determined by the fast load transient response once the output voltage ripple is no longer a problem. Capacitance satisfies the voltage overshoot during the transient response while also meeting the undershoot requirement, because the inductor discharging slew rate is slower when releasing load relative to the faster inductor charging slew rate when applying load step on output.

The output capacitance to maintain the overshoot voltage within a specified voltage change is expressed as:

Equation (11)

where the parameters are:ISTEP: Load step on outputL: Inductor valueΔV O : Output voltage change requirement of load transient responseV OUT : Regulated output voltage

Select the recommended output capacitance as in the data sheet per its inductor value to get an optimal phase margin.

Adjusting the Output Voltage

Output voltage is set either by the fixed internal resistor divider, or adjusted by the external resistor network, if applicable, with feedback to the switching regulator IC. The current IRT flowing through the top resistor RT should be larger than 100 times of the leakage current IFB going into the feedback pin of the IC to maintain voltage accuracy on the output. Add a small feedforward capacitor CFF in parallel with the top resistor RT to produce a boost zero in the feedback control loop to optimize phase margin.

Follow the data sheet to choose the recommended bottom resistor RB in Figure 3 as a smaller value in kΩ. Then, the top resistor RT is calculated as follows:

Equation (12)

where the parameters are:R B : Bottom resistor in adjustable resistor divider network as suggested from the data sheetV OUT : Desired output voltageV FB : Regulated feedback voltage

图 3.可调电阻分压器网络配置

功耗

在特定工况下，输出功率P外在给定输出电压 V 下固定外和负载电流 I 外 .功率损耗越小 P损失的效率η（η = P 外 ,(3 外 + P 损失 )).电感器的功率损耗包括直流导通损耗（I外 ^2^ × R 断续器 ）和交流磁芯损耗，这是由电感器在公式（13）中忽略的特定电感器功率模型上提供的。

开关稳压器IC上的功耗表示为：

等式 （13）

其中参数为：V 外 ： 稳压输出电压I 负荷 ： ICη所需的负载电流：稳压器R的效率 断续器 ： 电感直流电阻

器件内部的功耗转化为热量，增加结温。芯片 T 的结温J超过工作温度 T 的最大限值杰马克斯如数据手册所示，会降低使用寿命并影响产品可靠性。

要估计给定环境 TA 中的结温，请执行以下操作：

等式 （14）

其中参数为：T 一个 ： 环境温度Θ 断续器 ： 数据表P 中建议的结与环境温度的热阻 损失 ：公式（13）中器件内部的功率损耗

一些稳压器具有嵌入式芯片温度监控功能，无论稳压器在何种环境温度下工作，都可以直接在单个TEMP引脚上测量电压的方式指示结温。

当应用急需高功率电源时，电源开关稳压器解决方案的热管理具有挑战性。快速开关频率允许使用更紧凑的元件，以节省空间，以集成更多的功能解决方案，并在彼此之间引入更多的热传递。优化的 PCB 布局和热效率高的 IC 封装可冷却结温，使其更适合更高的环境工作条件。选择将功率平均分配到多个并联动力系上的多相配置可以缓解热压，而不是成为PCB上的热点，烧毁相邻元件。