代码1
always@(enable or ina or inb)
begin
if(enable) begin
data_out = ina;
end
else begin
data_out = inb;
end
end
代码2
input[3:0] data_in;
always@(data_in)
begin
case(data_in)
0 : out1 = 1'b1;
1,3 : out2 = 1'b1;
2,4,5,6,7 : out3 = 1'b1;
default: out4 = 1'b1;
endcase
end
答案是代码2在综合时更容易产生latch。