FPGA输出两路具有相位差的高频方波信号,怎样实现?用延时可以吗?怎么实现呢?我是这样做的,可是看不到效果呀!!!reg[1:0] state;
reg[30:0] cnt;
always @(posedge clk)
begin
case(state)
0 : begin cnt = 0; state = 1; end
1 : begin
cnt = cnt + 1;
if( cnt < 2500000 )
state = 1;
else state = 2;
end
2 : begin fb = count_r; end
default : cnt = 0;
endcase
end