芯来e203移植开发分享（一）——vcs+verdi仿真环境搭建

这里就不详细介绍蜂鸟e203，e203的仿真环境使用的是iverilog，一般工作中，主要使用的是vcs+verdi。个人觉得使用vcs的学习环境更为好一些。在这里简单分享一下。
代码准备

由于使用之后的开发板，并不是相应相应配套的开发板。所以这里只从e203中提取需要的RTL文件。建立一个自己习惯的工作目录，这里简单分享一下，我现在自己用的。FPGA的移植之后会分享给大家，欢迎大家持续关注。

·创建目录之后，我们在work目录下，编写makefile。
TESTCASE = ../tb/testcase/rv32ui-p-add DUMPWAVE = 1SIM_OPtiONS =  -full64  -R  +vc  +v2k  -sverilog -timescale=1ns/1ns -debug_acc+dmptfFSDB_OPTIONS = +DUMPWAVE=${DUMPWAVE} +define+vcsall    :   vcs         sim         verdirun    :    vcs simvcs :    vcs          ${SIM_OPTIONS} +TESTCASE=${TESTCASE} ${FSDB_OPTIONS}         -f tblist.f -f filelist.f  sim    :    ./simv -l sim.logverdi :    verdi -sv -f tblist.f -f filelist.f clean  :     rm  -rf  *~  core  csrc  simv*  vc_hdrs.h  ucli.key  urg* *.log  novas.* *.fsdb* verdiLog  64* DVEfiles *.vpd· 这里我使用tblist存放tb文件，tb文件还是使用e203原来给的tb文件，filelist存放rtl文件。可以存在同一个list文件，这看个人习惯。
tblist.f内容
+incdir+../tb../tb/tb_top.vfilelist.f内容
+incdir+../rtl/core +incdir+../rtl/perips/apb_i2c../rtl/soc/e203_soc_top.v../rtl/core/e203_biu.v../rtl/core/e203_clkgate.v../rtl/core/e203_clk_ctrl.v../rtl/core/e203_core.v../rtl/core/e203_cpu.v../rtl/core/e203_cpu_top.v../rtl/core/e203_dtcm_ctrl.v../rtl/core/e203_dtcm_ram.v../rtl/core/e203_extend_csr.v../rtl/core/e203_exu.v../rtl/core/e203_exu_alu.v../rtl/core/e203_exu_alu_bjp.v../rtl/core/e203_exu_alu_csrctrl.v../rtl/core/e203_exu_alu_dpath.v../rtl/core/e203_exu_alu_lsuagu.v../rtl/core/e203_exu_alu_muldiv.v../rtl/core/e203_exu_alu_rglr.v../rtl/core/e203_exu_branchslv.v../rtl/core/e203_exu_commit.v../rtl/core/e203_exu_csr.v../rtl/core/e203_exu_decode.v../rtl/core/e203_exu_disp.v../rtl/core/e203_exu_excp.v../rtl/core/e203_exu_longpwbck.v../rtl/core/e203_exu_nice.v../rtl/core/e203_exu_oitf.v../rtl/core/e203_exu_regfile.v../rtl/core/e203_exu_wbck.v../rtl/core/e203_ifu.v../rtl/core/e203_ifu_ifetch.v../rtl/core/e203_ifu_ift2icb.v../rtl/core/e203_ifu_litebpu.v../rtl/core/e203_ifu_minidec.v../rtl/core/e203_irq_sync.v../rtl/core/e203_itcm_ctrl.v../rtl/core/e203_itcm_ram.v../rtl/core/e203_lsu.v../rtl/core/e203_lsu_ctrl.v../rtl/core/e203_reset_ctrl.v../rtl/core/e203_srams.v../rtl/debug/sirv_debug_module.v../rtl/debug/sirv_debug_ram.v../rtl/debug/sirv_debug_rom.v../rtl/debug/sirv_jtag_dtm.v../rtl/debug/sirv_debug_csr.v../rtl/fab/sirv_icb1to16_bus.v../rtl/fab/sirv_icb1to2_bus.v../rtl/fab/sirv_icb1to8_bus.v../rtl/general/sirv_1cyc_sram_ctrl.v../rtl/general/sirv_gnrl_bufs.v../rtl/general/sirv_gnrl_dffs.v../rtl/general/sirv_gnrl_icbs.v../rtl/general/sirv_gnrl_ram.v../rtl/general/sirv_gnrl_xchecker.v../rtl/general/sirv_sim_ram.v../rtl/general/sirv_sram_icb_ctrl.v../rtl/mems/sirv_mrom.v../rtl/mems/sirv_mrom_top.v../rtl/perips/apb_adv_timer/adv_timer_apb_if.v../rtl/perips/apb_adv_timer/apb_adv_timer.v../rtl/perips/apb_adv_timer/comparator.v../rtl/perips/apb_adv_timer/input_stage.v../rtl/perips/apb_adv_timer/prescaler.v../rtl/perips/apb_adv_timer/timer_cntrl.v../rtl/perips/apb_adv_timer/timer_module.v../rtl/perips/apb_adv_timer/up_down_counter.v../rtl/perips/apb_uart/apb_uart.v../rtl/perips/apb_uart/io_generic_fifo.v../rtl/perips/apb_uart/uart_interrupt.v../rtl/perips/apb_uart/uart_rx.v../rtl/perips/apb_uart/uart_tx.v../rtl/perips/apb_gpio/apb_gpio.v../rtl/perips/apb_i2c/apb_i2c.v../rtl/perips/apb_i2c/i2c_master_bit_ctrl.v../rtl/perips/apb_i2c/i2c_master_byte_ctrl.v../rtl/perips/apb_spi_master/apb_spi_master.v../rtl/perips/apb_spi_master/spi_master_apb_if.v../rtl/perips/apb_spi_master/spi_master_clkgen.v../rtl/perips/apb_spi_master/spi_master_controller.v../rtl/perips/apb_spi_master/spi_master_fifo.v../rtl/perips/apb_spi_master/spi_master_rx.v../rtl/perips/apb_spi_master/spi_master_tx.v../rtl/perips/sirv_aon.v../rtl/perips/sirv_aon_lclkgen_regs.v../rtl/perips/sirv_aon_porrst.v../rtl/perips/sirv_aon_top.v../rtl/perips/sirv_aon_wrapper.v../rtl/perips/sirv_AsyncResetReg.v../rtl/perips/sirv_AsyncResetRegVec.v../rtl/perips/sirv_AsyncResetRegVec_1.v../rtl/perips/sirv_AsyncResetRegVec_129.v../rtl/perips/sirv_AsyncResetRegVec_36.v../rtl/perips/sirv_clint.v../rtl/perips/sirv_clint_top.v../rtl/perips/sirv_DeglitchShiftRegister.v../rtl/perips/sirv_expl_axi_slv.v../rtl/perips/sirv_flash_qspi.v../rtl/perips/sirv_flash_qspi_top.v../rtl/perips/sirv_hclkgen_regs.v../rtl/perips/sirv_jtaggpioport.v../rtl/perips/sirv_LevelGateway.v../rtl/perips/sirv_plic_man.v../rtl/perips/sirv_plic_top.v../rtl/perips/sirv_pmu.v../rtl/perips/sirv_pmu_core.v../rtl/perips/sirv_qspi_arbiter.v../rtl/perips/sirv_qspi_fifo.v../rtl/perips/sirv_qspi_media.v../rtl/perips/sirv_qspi_physical.v../rtl/perips/sirv_queue.v../rtl/perips/sirv_queue_1.v../rtl/perips/sirv_repeater_6.v../rtl/perips/sirv_ResetCatchAndSync.v../rtl/perips/sirv_ResetCatchAndSync_2.v../rtl/perips/sirv_rtc.v../rtl/perips/sirv_spi_flashmap.v../rtl/perips/sirv_tlfragmenter_qspi_1.v../rtl/perips/sirv_tlwidthwidget_qspi.v../rtl/perips/sirv_tl_repeater_5.v../rtl/perips/sirv_wdog.v../rtl/subsys/e203_subsys_clint.v../rtl/subsys/e203_subsys_gfcm.v../rtl/subsys/e203_subsys_hclkgen.v../rtl/subsys/e203_subsys_hclkgen_rstsync.v../rtl/subsys/e203_subsys_main.v../rtl/subsys/e203_subsys_mems.v../rtl/subsys/e203_subsys_nice_core.v../rtl/subsys/e203_subsys_perips.v../rtl/subsys/e203_subsys_plic.v../rtl/subsys/e203_subsys_pll.v../rtl/subsys/e203_subsys_pllclkdiv.v../rtl/subsys/e203_subsys_top.v · 同时TB中使用$value$plusargs(“xxx=%d”,xxx)语句，从外界传递参数。所以我们可以从，在makefile中设置具体TESTCASE的testcase的存放的路径，这里我们使用rv32ui-p-add.verilog，DUMPWAVE设置为1时，同时预编译VCS时，可以dump对应的.fsdb波形文件。
· 如此，我们使用make命令就可以执行具体仿真操作了，make verdi打开verdi,make run开始编译与仿真。