实验目的

熟悉PDS开发流程，掌握流水灯原理并实现流水灯

实验要求

设计8个LED以0.5s间隔接替点亮

实现代码

`define UD #1





module led_light(


    input               clk,   // input clock, the frequency is 40MHz


    input               rstn, // input reset signal, active at low  


    output [7:0]   led   // output LED control signal , lignting at high 


);


//==============================================================================





    reg [25:0] led_light_cnt;


    reg [ 7:0] led_status;




    //  time counter


    always @(posedge clk)


    begin


        if(!rstn)


            led_light_cnt <= `UD 26'd0;


        else if(led_light_cnt == 26'd19_999_999)


            led_light_cnt <= `UD 26'd0;


        else


            led_light_cnt <= `UD led_light_cnt + 26'd1; 


    end




    // led status change


    always @(posedge clk)


    begin


        if(!rstn)


            led_status <= `UD 8'd1;


        else if(led_light_cnt == 26'd19_999_999)


            //led_status <= `UD ~led_status;


            led_status <={led_status[6:0],led_status[7]};


    end





    assign led = led_status;




endmodule

学习收获

1-了解了盘古开发板

2-对国产FPGA有了新的认识

3-熟悉了PDS开发环境

4-对比了Verilog和C语言的不同

5-慢慢适应嵌入式开发和FPGA开发的不同