DSP初始驱动不对，其中一路驱动多了50%占空比是咋回事？

如题，Buck-boost电路，两路交错并联，PWM1为第一路，PWM2为第二路。上下管互补。任务中开启PWM，比较寄存器是中断里赋值。但实际驱动PWM1开机时总会多驱动50%，如下图，理论上两路PWM交错180度应该是差不多的，但第一路多驱动了50%。大佬们，怎么解？

开启PWM函数
void EnablePwm(void)
{
EPwm1Regs.AQCSFRC.bit.CSFA = 0;
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.AQCSFRC.bit.CSFA = 0;
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

}
PWM配置函数。
void InitEPwm1(void)
{
EPwm1Regs.TBPRD = 3000;
EPwm1Regs.TBPHS.half.TBPHS = 0;
EPwm1Regs.TBCTR = 0;

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;  
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;         
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;          
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;   
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;        
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;   
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

EPwm1Regs.AQCTLA.bit.CAU        = AQ_CLEAR;       
EPwm1Regs.AQCTLA.bit.CAD        = AQ_SET;         
EPwm1Regs.CMPA.half.CMPA = EPWM1_CMPA;          

EPwm1Regs.DBCTL.bit.IN_MODE     = DBA_ALL;
EPwm1Regs.DBCTL.bit.OUT_MODE    = DB_DISABLE;
EPwm1Regs.DBCTL.bit.POLSEL      = DB_ACTV_HIC;
EPwm1Regs.DBRED                 = EPWM1_TIME_DB;
EPwm1Regs.DBFED                 = EPWM1_TIME_DB;
EPwm1Regs.AQSFRC.all            = 0xC0;
EPwm1Regs.AQCSFRC.all           = 5; 

EPwm1Regs.ETSEL.bit.INTEN = 0; 
EALLOW;
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TZ1;
EPwm1Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_LOW;       
EPwm1Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1;
EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_SYNC;  

EPwm1Regs.DCTRIPSEL.bit.DCALCOMPSEL = DC_TZ2;
EPwm1Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAL_LOW;        
EPwm1Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2;
EPwm1Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_SYNC;  


EPwm1Regs.TZSEL.bit.OSHT1       = 1; 
EPwm1Regs.TZSEL.bit.OSHT2       = 1;

// EPwm1Regs.TZSEL.bit.OSHT3 = 1;
EPwm1Regs.TZCTL.bit.DCAEVT1 = TZ_NO_CHANGE;
EPwm1Regs.TZCTL.bit.DCAEVT2 = TZ_NO_CHANGE;
EPwm1Regs.TZCTL.bit.DCBEVT1 = TZ_NO_CHANGE;
EPwm1Regs.TZCTL.bit.DCBEVT2 = TZ_NO_CHANGE;
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;

EPwm1Regs.TZEINT.bit.OST = 1; 
EDIS;

}

void InitEPwm2(void)
{
EPwm2Regs.TBPRD = 3000;
EPwm2Regs.TBPHS.half.TBPHS = 3000;
EPwm2Regs.TBCTR = 0x0000;

EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW; 
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;

EPwm2Regs.CMPA.half.CMPA = EPWM2_CMPA;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm2Regs.DBRED = EPWM1_TIME_DB;
EPwm2Regs.DBFED = EPWM1_TIME_DB;
EPwm2Regs.AQSFRC.all = 0xC0;
EPwm2Regs.AQCSFRC.all = 5;

EPwm2Regs.ETSEL.bit.INTEN = 0;

EALLOW;

EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TZ1;
EPwm2Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_LOW;
EPwm2Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1;
EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_SYNC; //同锟斤拷锟斤拷锟斤拷

EPwm2Regs.DCTRIPSEL.bit.DCALCOMPSEL = DC_TZ2;
EPwm2Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAL_LOW;
EPwm2Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2;
EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_SYNC;

EPwm2Regs.TZSEL.bit.OSHT1 = 1;
EPwm2Regs.TZSEL.bit.OSHT2 = 1;

//    EPwm2Regs.TZSEL.bit.OSHT3       = 1; 
EPwm2Regs.TZCTL.bit.DCAEVT1 = TZ_NO_CHANGE;
EPwm2Regs.TZCTL.bit.DCAEVT2 = TZ_NO_CHANGE;
EPwm2Regs.TZCTL.bit.DCBEVT1 = TZ_NO_CHANGE;
EPwm2Regs.TZCTL.bit.DCBEVT2 = TZ_NO_CHANGE;
EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO;

EPwm2Regs.TZEINT.bit.OST = 1;
EDIS;

}