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王凯

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[经验]

HPM63xx 调整主频为648MHz及超频816MHz

环境:hpm6300evk

SDK: v1.0.0

结论:

  1. 改为官方标称最高 648MHz 主频
  2. 超频至 816MHz,连续运行7小时暂未见异常,HPM63xx系列应该是 HPM67xx系列的裁剪版,制程一样,个人猜应该能正常跑816MHz,产品应用自行测试稳定性。
  3. 如果超频过高导致死机,会导致JTAG无法连接,只能通过ISP重新烧写固件。

步骤一:根据DS手册,调高核心电压至 1.2v
3.png

void board_init( void )

{

pcfg_dcdc_set_voltage(HPM_PCFG, 1100);

改为

void board_init( void )

{

pcfg_dcdc_set_voltage(HPM_PCFG, 1200);

步骤二:调整CPU时钟源和AXI、AHB分频系数

void board_init_clock( void )

{

....

/*

  • Configure CPU0 to 480MHz
  • NOTE: The PLL2 is disabled by default, and it will be enabled automatically if
  • it is required by any nodes.
  • Here the PLl2 clock is enabled after switching CPU clock source to it

*/

clock_set_source_divider(clock_cpu0, clk_src_pll1_clk0, 1);

/* Configure PLL1_CLK0 Post Divider to 1.2 */

pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 1);

/* Configure PLL1 clock frequencey to 576MHz, the PLL1_CLK0 frequency =- 576MHz / 1.2 = 480MHz */

pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 576000000);

改为

#if 0

/*

  • Configure CPU0 to 480MHz
  • NOTE: The PLL2 is disabled by default, and it will be enabled automatically if
  • it is required by any nodes.
  • Here the PLl2 clock is enabled after switching CPU clock source to it

*/

clock_set_source_divider(clock_cpu0, clk_src_pll1_clk0, 1);

/* Configure PLL1_CLK0 Post Divider to 1.2 */

pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 1);

/* Configure PLL1 clock frequencey to 576MHz, the PLL1_CLK0 frequency =- 576MHz / 1.2 = 480MHz */

pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 576000000);

#else

#define BUS_FREQ_MAX (166000000UL)

#define CORE0_FREQ_HZ (816000000UL)

pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 0);

uint32_t expected_freq = CORE0_FREQ_HZ;

uint32_t axi_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX;

uint32_t ahb_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX;

sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clk_src_pll1_clk0, 1, axi_sub_div, ahb_sub_div);

pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, CORE0_FREQ_HZ);

#undef BUS_FREQ_MAX

#undef CORE0_FREQ_HZ

#endif

注意点,AXI和AHB主频不超166MHz,详见DS手册(下图)

4.png

超频变砖解决办法:

  1. 先把板上的 Boot0 = 0, Boot1 = 1,重启电源 进入ISP模式。
  2. 用 HPMProgrammmer_v0.3.0 将降频后的新固件烧写进去即可

回帖(1)

martin330824

2023-6-4 20:29:45
芯片最好还是按厂家的datasheet使用。
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