在spi1上加两个595怎么更改设备树呀

在spi1上加两个595，同spi4 一样的，怎么更改设备树呀？
      spi4 {
            compatible = "spi-gpio";
            pinctrl-names = "default";
            pinctrl-0 = <&pinctrl_spi4>;
            pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
            status = "okay";
            gpio-sck = <&gpio5 11 0>;
            gpio-mosi = <&gpio5 10 0>;
            cs-gpios = <&gpio5 7 0>;
            num-chipselects = <1>;
            #address-cells = <1>;
            #size-cells = <0>;

            gpio_spi: gpio_spi@0 {
                     compatible = "fairchild,74hc595";
                     gpio-controller;
                     #gpio-cells = <2>;
                     reg = <0>;
                     registers-number = <1>;
                     registers-default = /bits/ 8 <0xa7>;
                     spi-max-frequency = <100000>;
            };
      };

registers-default = /bits/ 16 <0x00a7>;
因为我是两片，这个地方是不是要改成16？
我用 cat /sys/kernel/debug/gpio，怎么是空的，查不到gpio

root@freescale ~$ mount -t debugfs none /sys/kernel/debug
root@freescale ~$  cat /sys/kernel/debug/gpio
GPIOs 0-31, platform/209c000.gpio, 209c000.gpio:
gpio-9 (led2             ) out lo
gpio-19  (2190000.usdhc cd ) in  hi

GPIOs 32-63, platform/20a0000.gpio, 20a0000.gpio:

GPIOs 64-95, platform/20a4000.gpio, 20a4000.gpio:
gpio-66  (u***_otg1_vbus    ) out lo

GPIOs 96-127, platform/20a8000.gpio, 20a8000.gpio:

GPIOs 128-159, platform/20ac000.gpio, 20ac000.gpio:
gpio-128 (GTP RST PORT       ) in  hi
gpio-129 (GTP INT IRQ       ) in  hi
gpio-131 (?                ) out lo
gpio-133 (heartbeat          ) out lo
gpio-135 (spi32766.0       ) out lo
gpio-136 (?                ) out lo
gpio-137 (led1             ) out lo
gpio-138 (spi4.15          ) out lo
gpio-139 (spi4.15          ) out lo

李维兴

2022-1-10 13:49:03

先参考应用笔记添加spi1，再参考spi4添加74hc595

谭军红

2022-1-10 13:49:21

路径应该是/sys/class/gpio/吧，ls /sys/class/gpio/查看

杨春林

2022-1-10 13:50:02

GPIOs 248-255, spi/spi32766.0, 74hc595, can sleep:
挂载后能看到GPIO的信息了，可我的SPI1下接的595没有看到，我的设备树是这样改的

      spi4 {
            compatible = "spi-gpio";
            pinctrl-names = "default";
            pinctrl-0 = <&pinctrl_spi4>;
            pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; //NOE
            status = "okay";
            gpio-sck = <&gpio5 11 0>; //SHCP
            gpio-mosi = <&gpio5 10 0>; //SDI
            cs-gpios = <&gpio5 7 0>;    //STCP
            num-chipselects = <1>;
            #address-cells = <1>;
            #size-cells = <0>;

            gpio_spi: gpio_spi@0 {
                     compatible = "fairchild,74hc595";
                     gpio-controller;
                     #gpio-cells = <2>;
                     reg = <0>;
                     registers-number = <1>;
                     registers-default = /bits/ 8 <0xa7>;
                     spi-max-frequency = <100000>;
            };
      };
      /*新增GPIO SPI1*/
      spi1 {
            compatible = "spi-gpio";
            pinctrl-names = "default";
            pinctrl-0 = <&pinctrl_spi1>;
            //pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; OE固定接低
            status = "okay";
            gpio-sck = <&gpio4 25 0>;
            gpio-mosi = <&gpio4 27 0>;
            cs-gpios = <&gpio4 26 0>;
            num-chipselects = <1>;
            #address-cells = <1>;
            #size-cells = <0>;

            gpio_spi1: gpio_spi1@0 {
                     compatible = "fairchild,74hc595";
                     gpio-controller;
                     #gpio-cells = <2>;
                     reg = <0>;
                     registers-number = <1>;
                     registers-default = /bits/ 16 <0x00a7>;
                     spi-max-frequency = <100000>;
            };
      };

      /*新增GPIO SPi1*/
      pinctrl_spi1: spi1grp {
                     fsl,pins = <
                              MX6UL_PAD_CSI_DATA06__GPIO4_IO27       0x70a1
                              MX6UL_PAD_CSI_DATA05__GPIO4_IO26       0x70a1
                              MX6UL_PAD_CSI_DATA04__GPIO4_IO25       0x70a1
                              MX6UL_PAD_CSI_DATA07__GPIO4_IO28       0x70a1
                     >;
            };

刘桂珍

2022-1-10 13:50:37

去掉SN74HC595芯片，以其中的修改为参考添加芯片

张涛

回帖（4）

李维兴

谭军红

杨春林

刘桂珍

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