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ADAU1781具有哪些特性参数应用?

本文介绍了ADAU1781主要特性,方框图以及差分输入系统,模拟麦克风输入系统, 单端立体声线输入框图和立体声数字麦克风输入系统的框图,评估板EVAL-ADAU1781Z主要特性,框图,电路图,材料清单和PCB元件布局图。

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2021-6-2 17:10:58
  ADI公司的ADAU1781是低功耗24位立体声编译码器,可编程的SigmaDSP音频处理核,低噪音DAC和ADC支持取样速率从8kHz到96kHz,扬声器能向8欧姆负载输出400mW,模拟和数字I/O电压1.8 V- 3.3 V,主要用在数码相机和数码摄像机。本文介绍了ADAU1781主要特性,方框图以及差分输入系统,模拟麦克风输入系统, 单端立体声线输入框图和立体声数字麦克风输入系统的框图,评估板EVAL-ADAU1781Z主要特性,框图,电路图,材料清单和PCB元件布局图。
  The ADAU1781 is a low power, 24-bit stereo audio codec. The low noise DAC and ADC support sample rates from 8 kHz to 96 kHz. Low current draw and power saving modes make the ADAU1781 ideal for battery-powered audio applications.
  A programmable SigmaDSP® core provides enhanced record and playback processing to improve overall audio quality.
  The record path includes two digital stereo microphone inputs and an analog stereo input path. The analog inputs can be configured for either a pseudo differential or a single-ended stereo source. A dedicated analog beep input signal can be mixed into any output path. The ADAU1781 includes a stereo line output and speaker driver, which makes the device capable of supporting dynamic speakers.
  The serial control bus supports the I2C® or SPI protocols, and the serial audio bus is programmable for I2S, left-justified, right-justified, or TDM mode. A programmable PLL supports flexible clock generation for all standard rates and available master clocks from 11 MHz to 20 MHz
  ADAU1781主要特性:
  24-bit stereo audio ADC and DAC
  400 mW speaker amplifier (into 8 Ω load)
  Programmable SigmaDSP audio processing core
  Wind noise detection and filtering
  Enhanced stereo capture (ESC)
  Dynamics processing
  Equalization and filtering
  Volume control and mute
  Sampling rates from 8 kHz to 96 kHz
  Stereo pseudo differential microphone input
  Optional stereo digital microphone input pulse-density modulation (PDM)
  Stereo line output
  PLL supporting a range of input clock rates
  Analog and digital I/O 1.8 V to 3.3 V
  Software control via SigmaStudio graphical user interface
  Software-controllable, clickless mute
  Software register and hardware pin standby mode
  32-lead, 5 mm × 5 mm LFCSP
  ADAU1781应用:
  Digital still cameras
  Digital video cameras
  20120503105910740.gif
  图1. ADAU1781框图
  20120503105911288.gif
  图2. ADAU1781差分输入系统框图
  20120503105911313.gif
  图3. ADAU1781模拟麦克风输入系统框图
  20120503105912584.gif
  图4. ADAU1781单端立体声线输入系统框图
  2012050310591224.gif
  图5. ADAU1781立体声数字麦克风输入系统框图
  ADAU1781 SigmaDSP评估板EVAL-ADAU1781Z
  This user guide explains the design and setup of the ADAU1781 SigmaDSP® evaluation board.
  This evaluation board provides full access to all analog and digital I/Os on the ADAU1781. The SigmaDSP is controlled by Analog Devices, Inc., SigmaStudio™ software, which interfaces to the board via a USB connection. This evaluation board can be powered either over the USB bus or by a single 3.8 V to 6 V supply, which is regulated to the voltages required on the board. The PC board is a 4-layer design, with a single ground plane and a single power plane on the inner layers. The board contains on-board microphones and speaker, and connectors for external microphones and speaker. The master clock can be provided externally or by the on-board 12.288 MHz active oscillator.
  EVAL-ADAU1781Z评估包包括:
  ADAU1781 evaluation board
  EVAL-ADUSB2EBZ (USBi) communications adapter
  USB cable with Mini-B plug
  Evaluation board/software quick-start guide
  20120503105913284.gif
  20120503105913685.gif
  图6.评估板EVAL-ADAU1781Z外形图
  20120503105915902.gif
  图7.评估板EVAL-ADAU1781Z功能框图
  20120503105915345.gif
  图8.评估板EVAL-ADAU1781Z电路图: SigmaDSP,模拟I/O和主时钟发生
  20120503105916793.gif
  图9.评估板EVAL-ADAU1781Z电路图:数字麦克风接口
  20120503105916194.gif
  图10.评估板EVAL-ADAU1781Z电路图:串行音频数据接口
  20120503105916786.gif
  图11.评估板EVAL-ADAU1781Z电路图:电源
  20120503105917597.gif
  图12.评估板EVAL-ADAU1781Z电路图:GPIO
  20120503105917818.gif
  图13.评估板EVAL-ADAU1781Z电路图:通信接口
  评估板EVAL-ADAU1781Z材料清单:
  20120503105918594.gif
  20120503105918933.gif
  20120503105919121.gif
  图14.评估板EVAL-ADAU1781Z PCB元件布局图
  详情请见:
  ADAU1781[2].pdf(1014.96 KB)2012-5-3 13:48 上传
  -1
  和
  UG-177[2].pdf(1.19 MB)2012-5-3 13:50 上传
  -1
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