library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder8 is
port(a,b:in std_logic_vector(7 downto 0);
cin:in std_logic;
sum:out std_logic_vector(7 downto 0);
cout:out std_logic);
end;
architecture bhv of adder8 is
signal a0,b0,cin0,s:std_logic_vector(8 downto 0);
begin
a0<=’0’&a;b0<=’0’&b;cin0<="00000000"&cin;
s<=a0+b0+cin0;
sum<=s(7 downto 0);
cout<=s(8);
end;
出现Error: Text Design File syntax error: Text Design File contains a symbolic name where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected 的错误，该如何解决
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