引用: bei232 发表于 2020-5-23 03:25
你好!
经与我们的硬件工程师确认,我们的板卡未改版前你说的两个管脚接一起确实是接一起的,请问接一起会造成该问题吗?什么原因了?
还有,后来我们的板卡又改了一版,就未接一起了。在改版上的板卡上就未出现该问题!如果真与硬件两个管脚接一起有关?那软件上有没有办法解决啊?谢谢 ...
按照手册上来,软件没法解决。
To most of the device, reset is de-asserted only when the POR and RESET pins are both
de-asserted (driven high). Therefore, in the sequence described above, if the RESET pin is
held low past the low period of the POR pin, most of the device will remain in reset. The only
exception being that PLL2 is taken out of reset as soon as POR is de-asserted (driven high),
regardless of the state of the RESET pin. The RESET pin should not be tied together with
the POR pin.
http://www.ti.com/lit/ds/symlink/tms320c6455.pdf
引用: bei232 发表于 2020-5-23 03:25
你好!
经与我们的硬件工程师确认,我们的板卡未改版前你说的两个管脚接一起确实是接一起的,请问接一起会造成该问题吗?什么原因了?
还有,后来我们的板卡又改了一版,就未接一起了。在改版上的板卡上就未出现该问题!如果真与硬件两个管脚接一起有关?那软件上有没有办法解决啊?谢谢 ...
按照手册上来,软件没法解决。
To most of the device, reset is de-asserted only when the POR and RESET pins are both
de-asserted (driven high). Therefore, in the sequence described above, if the RESET pin is
held low past the low period of the POR pin, most of the device will remain in reset. The only
exception being that PLL2 is taken out of reset as soon as POR is de-asserted (driven high),
regardless of the state of the RESET pin. The RESET pin should not be tied together with
the POR pin.
http://www.ti.com/lit/ds/symlink/tms320c6455.pdf
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