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[经验]

VHDL实现基于寄存器的FIFO




无AF,AE标志的FIFO
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;

  5. entity module_fifo_regs_no_flags is
  6.   generic (
  7.     g_WIDTH : natural := 8;
  8.     g_DEPTH : integer := 32
  9.     );
  10.   port (
  11.     i_rst_sync : in std_logic;
  12.     i_clk      : in std_logic;

  14.     -- FIFO Write Interface
  15.     i_wr_en   : in  std_logic;
  16.     i_wr_data : in  std_logic_vector(g_WIDTH-1 downto 0);
  17.     o_full    : out std_logic;

  19.     -- FIFO Read Interface
  20.     i_rd_en   : in  std_logic;
  21.     o_rd_data : out std_logic_vector(g_WIDTH-1 downto 0);
  22.     o_empty   : out std_logic
  23.     );
  24. end module_fifo_regs_no_flags;

  26. architecture rtl of module_fifo_regs_no_flags is

  28.   type t_FIFO_DATA is array (0 to g_DEPTH-1) of std_logic_vector(g_WIDTH-1 downto 0);
  29.   signal r_FIFO_DATA : t_FIFO_DATA := (others => (others => '0'));

  31.   signal r_WR_INDEX   : integer range 0 to g_DEPTH-1 := 0;
  32.   signal r_RD_INDEX   : integer range 0 to g_DEPTH-1 := 0;

  34.   -- # Words in FIFO, has extra range to allow for assert conditions
  35.   signal r_FIFO_COUNT : integer range -1 to g_DEPTH+1 := 0;

  37.   signal w_FULL  : std_logic;
  38.   signal w_EMPTY : std_logic;
  39.    
  40. begin

  42.   p_CONTROL : process (i_clk) is
  43.   begin
  44.     if rising_edge(i_clk) then
  45.       if i_rst_sync = '1' then
  46.         r_FIFO_COUNT <= 0;
  47.         r_WR_INDEX   <= 0;
  48.         r_RD_INDEX   <= 0;
  49.       else

  51.         -- Keeps track of the total number of words in the FIFO
  52.         if (i_wr_en = '1' and i_rd_en = '0') then
  53.           r_FIFO_COUNT <= r_FIFO_COUNT + 1;
  54.         elsif (i_wr_en = '0' and i_rd_en = '1') then
  55.           r_FIFO_COUNT <= r_FIFO_COUNT - 1;
  56.         end if;

  58.         -- Keeps track of the write index (and controls roll-over)
  59.         if (i_wr_en = '1' and w_FULL = '0') then
  60.           if r_WR_INDEX = g_DEPTH-1 then
  61.             r_WR_INDEX <= 0;
  62.           else
  63.             r_WR_INDEX <= r_WR_INDEX + 1;
  64.           end if;
  65.         end if;

  67.         -- Keeps track of the read index (and controls roll-over)        
  68.         if (i_rd_en = '1' and w_EMPTY = '0') then
  69.           if r_RD_INDEX = g_DEPTH-1 then
  70.             r_RD_INDEX <= 0;
  71.           else
  72.             r_RD_INDEX <= r_RD_INDEX + 1;
  73.           end if;
  74.         end if;

  76.         -- Registers the input data when there is a write
  77.         if i_wr_en = '1' then
  78.           r_FIFO_DATA(r_WR_INDEX) <= i_wr_data;
  79.         end if;
  80.          
  81.       end if;                           -- sync reset
  82.     end if;                             -- rising_edge(i_clk)
  83.   end process p_CONTROL;
  84.    
  85.   o_rd_data <= r_FIFO_DATA(r_RD_INDEX);

  87.   w_FULL  <= '1' when r_FIFO_COUNT = g_DEPTH else '0';
  88.   w_EMPTY <= '1' when r_FIFO_COUNT = 0       else '0';

  90.   o_full  <= w_FULL;
  91.   o_empty <= w_EMPTY;
  92.    
  93.   -- ASSERTION LOGIC - Not synthesized
  94.   -- synthesis translate_off

  96.   p_ASSERT : process (i_clk) is
  97.   begin
  98.     if rising_edge(i_clk) then
  99.       if i_wr_en = '1' and w_FULL = '1' then
  100.         report "ASSERT FAILURE - MODULE_REGISTER_FIFO: FIFO IS FULL AND BEING WRITTEN " severity failure;
  101.       end if;

  103.       if i_rd_en = '1' and w_EMPTY = '1' then
  104.         report "ASSERT FAILURE - MODULE_REGISTER_FIFO: FIFO IS EMPTY AND BEING READ " severity failure;
  105.       end if;
  106.     end if;
  107.   end process p_ASSERT;

  109.   -- synthesis translate_on
  110. end rtl;
该版本的Testbench文件
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;

  5. entity module_fifo_regs_no_flags_tb is
  6. end module_fifo_regs_no_flags_tb;

  8. architecture behave of module_fifo_regs_no_flags_tb is

  10.   constant c_DEPTH : integer := 4;
  11.   constant c_WIDTH : integer := 8;
  12.    
  13.   signal r_RESET   : std_logic := '0';
  14.   signal r_CLOCK   : std_logic := '0';
  15.   signal r_WR_EN   : std_logic := '0';
  16.   signal r_WR_DATA : std_logic_vector(c_WIDTH-1 downto 0) := X"A5";
  17.   signal w_FULL    : std_logic;
  18.   signal r_RD_EN   : std_logic := '0';
  19.   signal w_RD_DATA : std_logic_vector(c_WIDTH-1 downto 0);
  20.   signal w_EMPTY   : std_logic;
  21.    
  22.   component module_fifo_regs_no_flags is
  23.     generic (
  24.       g_WIDTH : natural := 8;
  25.       g_DEPTH : integer := 32
  26.       );
  27.     port (
  28.       i_rst_sync : in std_logic;
  29.       i_clk      : in std_logic;

  31.       -- FIFO Write Interface
  32.       i_wr_en   : in  std_logic;
  33.       i_wr_data : in  std_logic_vector(g_WIDTH-1 downto 0);
  34.       o_full    : out std_logic;

  36.       -- FIFO Read Interface
  37.       i_rd_en   : in  std_logic;
  38.       o_rd_data : out std_logic_vector(g_WIDTH-1 downto 0);
  39.       o_empty   : out std_logic
  40.       );
  41.   end component module_fifo_regs_no_flags;

  43.    
  44. begin

  46.   MODULE_FIFO_REGS_NO_FLAGS_INST : module_fifo_regs_no_flags
  47.     generic map (
  48.       g_WIDTH => c_WIDTH,
  49.       g_DEPTH => c_DEPTH
  50.       )
  51.     port map (
  52.       i_rst_sync => r_RESET,
  53.       i_clk      => r_CLOCK,
  54.       i_wr_en    => r_WR_EN,
  55.       i_wr_data  => r_WR_DATA,
  56.       o_full     => w_FULL,
  57.       i_rd_en    => r_RD_EN,
  58.       o_rd_data  => w_RD_DATA,
  59.       o_empty    => w_EMPTY
  60.       );


  63.   r_CLOCK <= not r_CLOCK after 5 ns;

  65.   p_TEST : process is
  66.   begin
  67.     wait until r_CLOCK = '1';
  68.     r_WR_EN <= '1';
  69.     wait until r_CLOCK = '1';
  70.     wait until r_CLOCK = '1';
  71.     wait until r_CLOCK = '1';
  72.     wait until r_CLOCK = '1';
  73.     r_WR_EN <= '0';
  74.     r_RD_EN <= '1';
  75.     wait until r_CLOCK = '1';
  76.     wait until r_CLOCK = '1';
  77.     wait until r_CLOCK = '1';
  78.     wait until r_CLOCK = '1';
  79.     r_RD_EN <= '0';
  80.     r_WR_EN <= '1';
  81.     wait until r_CLOCK = '1';
  82.     wait until r_CLOCK = '1';
  83.     r_RD_EN <= '1';
  84.     wait until r_CLOCK = '1';
  85.     wait until r_CLOCK = '1';
  86.     wait until r_CLOCK = '1';
  87.     wait until r_CLOCK = '1';
  88.     wait until r_CLOCK = '1';
  89.     wait until r_CLOCK = '1';
  90.     wait until r_CLOCK = '1';
  91.     wait until r_CLOCK = '1';
  92.     r_WR_EN <= '0';
  93.     wait until r_CLOCK = '1';
  94.     wait until r_CLOCK = '1';
  95.     wait until r_CLOCK = '1';
  96.     wait until r_CLOCK = '1';

  98.   end process;
  99.    
  100.    
  101. end behave;

加入AF和AE的FIFO
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;

  5. entity module_fifo_regs_with_flags is
  6.   generic (
  7.     g_WIDTH    : natural := 8;
  8.     g_DEPTH    : integer := 32;
  9.     g_AF_LEVEL : integer := 28;
  10.     g_AE_LEVEL : integer := 4
  11.     );
  12.   port (
  13.     i_rst_sync : in std_logic;
  14.     i_clk      : in std_logic;

  16.     -- FIFO Write Interface
  17.     i_wr_en   : in  std_logic;
  18.     i_wr_data : in  std_logic_vector(g_WIDTH-1 downto 0);
  19.     o_af      : out std_logic;
  20.     o_full    : out std_logic;

  22.     -- FIFO Read Interface
  23.     i_rd_en   : in  std_logic;
  24.     o_rd_data : out std_logic_vector(g_WIDTH-1 downto 0);
  25.     o_ae      : out std_logic;
  26.     o_empty   : out std_logic
  27.     );
  28. end module_fifo_regs_with_flags;

  30. architecture rtl of module_fifo_regs_with_flags is

  32.   type t_FIFO_DATA is array (0 to g_DEPTH-1) of std_logic_vector(g_WIDTH-1 downto 0);
  33.   signal r_FIFO_DATA : t_FIFO_DATA := (others => (others => '0'));

  35.   signal r_WR_INDEX   : integer range 0 to g_DEPTH-1 := 0;
  36.   signal r_RD_INDEX   : integer range 0 to g_DEPTH-1 := 0;

  38.   -- # Words in FIFO, has extra range to allow for assert conditions
  39.   signal r_FIFO_COUNT : integer range -1 to g_DEPTH+1 := 0;

  41.   signal w_FULL  : std_logic;
  42.   signal w_EMPTY : std_logic;
  43.    
  44. begin

  46.   p_CONTROL : process (i_clk) is
  47.   begin
  48.     if rising_edge(i_clk) then
  49.       if i_rst_sync = '1' then
  50.         r_FIFO_COUNT <= 0;
  51.         r_WR_INDEX   <= 0;
  52.         r_RD_INDEX   <= 0;
  53.       else

  55.         -- Keeps track of the total number of words in the FIFO
  56.         if (i_wr_en = '1' and i_rd_en = '0') then
  57.           r_FIFO_COUNT <= r_FIFO_COUNT + 1;
  58.         elsif (i_wr_en = '0' and i_rd_en = '1') then
  59.           r_FIFO_COUNT <= r_FIFO_COUNT - 1;
  60.         end if;

  62.         -- Keeps track of the write index (and controls roll-over)
  63.         if (i_wr_en = '1' and w_FULL = '0') then
  64.           if r_WR_INDEX = g_DEPTH-1 then
  65.             r_WR_INDEX <= 0;
  66.           else
  67.             r_WR_INDEX <= r_WR_INDEX + 1;
  68.           end if;
  69.         end if;

  71.         -- Keeps track of the read index (and controls roll-over)        
  72.         if (i_rd_en = '1' and w_EMPTY = '0') then
  73.           if r_RD_INDEX = g_DEPTH-1 then
  74.             r_RD_INDEX <= 0;
  75.           else
  76.             r_RD_INDEX <= r_RD_INDEX + 1;
  77.           end if;
  78.         end if;

  80.         -- Registers the input data when there is a write
  81.         if i_wr_en = '1' then
  82.           r_FIFO_DATA(r_WR_INDEX) <= i_wr_data;
  83.         end if;
  84.          
  85.       end if;                           -- sync reset
  86.     end if;                             -- rising_edge(i_clk)
  87.   end process p_CONTROL;

  89.    
  90.   o_rd_data <= r_FIFO_DATA(r_RD_INDEX);

  92.   w_FULL  <= '1' when r_FIFO_COUNT = g_DEPTH else '0';
  93.   w_EMPTY <= '1' when r_FIFO_COUNT = 0       else '0';

  95.   o_af <= '1' when r_FIFO_COUNT > g_AF_LEVEL else '0';
  96.   o_ae <= '1' when r_FIFO_COUNT < g_AE_LEVEL else '0';
  97.    
  98.   o_full  <= w_FULL;
  99.   o_empty <= w_EMPTY;
  100.    

  102.   -----------------------------------------------------------------------------
  103.   -- ASSERTION LOGIC - Not synthesized
  104.   -----------------------------------------------------------------------------
  105.   -- synthesis translate_off

  107.   p_ASSERT : process (i_clk) is
  108.   begin
  109.     if rising_edge(i_clk) then
  110.       if i_wr_en = '1' and w_FULL = '1' then
  111.         report "ASSERT FAILURE - MODULE_REGISTER_FIFO: FIFO IS FULL AND BEING WRITTEN " severity failure;
  112.       end if;

  114.       if i_rd_en = '1' and w_EMPTY = '1' then
  115.         report "ASSERT FAILURE - MODULE_REGISTER_FIFO: FIFO IS EMPTY AND BEING READ " severity failure;
  116.       end if;
  117.     end if;
  118.   end process p_ASSERT;

  120.   -- synthesis translate_on
  121.      
  122.    
  123. end rtl;
该版本的Testbench文件
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;

  5. entity module_fifo_regs_with_flags_tb is
  6. end module_fifo_regs_with_flags_tb;

  8. architecture behave of module_fifo_regs_with_flags_tb is

  10.   constant c_DEPTH    : integer := 4;
  11.   constant c_WIDTH    : integer := 8;
  12.   constant c_AF_LEVEL : integer := 2;
  13.   constant c_AE_LEVEL : integer := 2;

  15.   signal r_RESET   : std_logic := '0';
  16.   signal r_CLOCK   : std_logic := '0';
  17.   signal r_WR_EN   : std_logic := '0';
  18.   signal r_WR_DATA : std_logic_vector(c_WIDTH-1 downto 0) := X"A5";
  19.   signal w_AF      : std_logic;
  20.   signal w_FULL    : std_logic;
  21.   signal r_RD_EN   : std_logic := '0';
  22.   signal w_RD_DATA : std_logic_vector(c_WIDTH-1 downto 0);
  23.   signal w_AE      : std_logic;
  24.   signal w_EMPTY   : std_logic;
  25.    
  26.   component module_fifo_regs_with_flags is
  27.     generic (
  28.       g_WIDTH    : natural := 8;
  29.       g_DEPTH    : integer := 32;
  30.       g_AF_LEVEL : integer := 28;
  31.       g_AE_LEVEL : integer := 4
  32.       );
  33.     port (
  34.       i_rst_sync : in std_logic;
  35.       i_clk      : in std_logic;

  37.       -- FIFO Write Interface
  38.       i_wr_en   : in  std_logic;
  39.       i_wr_data : in  std_logic_vector(g_WIDTH-1 downto 0);
  40.       o_af      : out std_logic;
  41.       o_full    : out std_logic;

  43.       -- FIFO Read Interface
  44.       i_rd_en   : in  std_logic;
  45.       o_rd_data : out std_logic_vector(g_WIDTH-1 downto 0);
  46.       o_ae      : out std_logic;
  47.       o_empty   : out std_logic
  48.       );
  49.   end component module_fifo_regs_with_flags;

  51.    
  52. begin

  54.   MODULE_FIFO_REGS_WITH_FLAGS_INST : module_fifo_regs_with_flags
  55.     generic map (
  56.       g_WIDTH    => c_WIDTH,
  57.       g_DEPTH    => c_DEPTH,
  58.       g_AF_LEVEL => c_AF_LEVEL,
  59.       g_AE_LEVEL => c_AE_LEVEL
  60.       )
  61.     port map (
  62.       i_rst_sync => r_RESET,
  63.       i_clk      => r_CLOCK,
  64.       i_wr_en    => r_WR_EN,
  65.       i_wr_data  => r_WR_DATA,
  66.       o_af       => w_AF,
  67.       o_full     => w_FULL,
  68.       i_rd_en    => r_RD_EN,
  69.       o_rd_data  => w_RD_DATA,
  70.       o_ae       => w_AE,
  71.       o_empty    => w_EMPTY
  72.       );

  74.   r_CLOCK <= not r_CLOCK after 5 ns;

  76.   p_TEST : process is
  77.   begin
  78.     wait until r_CLOCK = '1';
  79.     r_WR_EN <= '1';
  80.     wait until r_CLOCK = '1';
  81.     wait until r_CLOCK = '1';
  82.     wait until r_CLOCK = '1';
  83.     wait until r_CLOCK = '1';
  84.     r_WR_EN <= '0';
  85.     r_RD_EN <= '1';
  86.     wait until r_CLOCK = '1';
  87.     wait until r_CLOCK = '1';
  88.     wait until r_CLOCK = '1';
  89.     wait until r_CLOCK = '1';
  90.     r_RD_EN <= '0';
  91.     r_WR_EN <= '1';
  92.     wait until r_CLOCK = '1';
  93.     wait until r_CLOCK = '1';
  94.     r_RD_EN <= '1';
  95.     wait until r_CLOCK = '1';
  96.     wait until r_CLOCK = '1';
  97.     wait until r_CLOCK = '1';
  98.     wait until r_CLOCK = '1';
  99.     wait until r_CLOCK = '1';
  100.     wait until r_CLOCK = '1';
  101.     wait until r_CLOCK = '1';
  102.     wait until r_CLOCK = '1';
  103.     r_WR_EN <= '0';
  104.     wait until r_CLOCK = '1';
  105.     wait until r_CLOCK = '1';
  106.     wait until r_CLOCK = '1';
  107.     wait until r_CLOCK = '1';

  109.   end process;
  110.    
  111. end behave;


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