tify;text-indent: 40px;">你好
我在Digilent公司使用BASYS2
和研究环境光传感器Pmod。
我想下面的代码信息
clk:50Mhz
sclk:1Mhz
cs:sclk x 16计数
数据8bit(dout是1位数据)
LED:通过环境光传感器输出和检查信息
我的源代码如下。
但它不适用于BASYS2板。
我不知道什么是错误。
所以请一些信息或建议
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL;
ENTITY SPI3 ISPORT(clk:IN std_logic; clr:IN std_logic; dout:IN std_logic; led:OUT std_logic_vector(7 DOWNTO 0); sclk:OUT std_logic; cs:OUT std_logic); END SPI3;
SPI3的架构SPI3_be
TYPE state_type IS(idle,adc_r,adc_w); SIGNAL状态:state_type:= idle;
SIGNAL cnt_sclk:INTEGER RANGE 0到49; SIGNAL newsclk:std_logic:='0'; SIGNAL cnt_cs:INTEGER RANGE 0到1599; SIGNAL newcs:std_logic:='1'; SIGNAL数据:std_logic_vector(7 DOWNTO 0); SIGNAL cnt_data
:INTEGER范围1到16; BEGINsclk csIF newcs ='1'THENstate ELSIF newcs ='0'THENstate END IF; WHEN adc_r => IF cnt_data> 0 AND cnt_data cnt_data state ELSIF cnt_data> 3 AND cnt_data cnt_data data(11 - cnt_data)
state ELSIF cnt_data> 11 AND cnt_data cnt_data state ELSIF cnt_data = 16 THENstate END IF; WHEN adc_w => led cnt_data state 以下为原文
Hello
I'm using BASYS2 at Digilent Co.
and Studying Ambient Light Sensor Pmod.
I think below information of code
clk : 50Mhz
sclk : 1Mhz
cs : sclk x 16 count
data 8bit ( dout is 1bit data)
LED : output and check of information by Ambient Light Sensor
My source code is below.
but it's not working on BASYS2 board.
I don't know what is error . So Please some imformation or advice
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY SPI3 IS
PORT(
clk : IN std_logic;
clr : IN std_logic;
dout : IN std_logic;
led : OUT std_logic_vector( 7 DOWNTO 0 );
sclk : OUT std_logic;
cs : OUT std_logic
);
END SPI3;
ARCHITECTURE SPI3_be OF SPI3 IS
TYPE state_type IS( idle, adc_r, adc_w );
SIGNAL state : state_type := idle;
SIGNAL cnt_sclk : INTEGER RANGE 0 TO 49;
SIGNAL newsclk : std_logic := '0';
SIGNAL cnt_cs : INTEGER RANGE 0 TO 1599;
SIGNAL newcs : std_logic := '1';
SIGNAL data : std_logic_vector( 7 DOWNTO 0 );
SIGNAL cnt_data : INTEGER RANGE 1 TO 16;
BEGIN
sclk <= newsclk;
cs <= newcs;
clkdiv : PROCESS( clr, clk )
BEGIN
IF clr = '0' THEN
cnt_sclk <= 0;
cnt_cs <= 0;
newsclk <= '0';
newcs <= '1';
ELSIF clk'EVENT AND clk = '1' THEN
IF cnt_sclk = 49 THEN
newsclk <= NOT newsclk;
cnt_sclk <= 0;
ELSE
cnt_sclk <= cnt_sclk + 1;
END IF;
IF cnt_cs = 1599 THEN
newcs <= NOT newcs;
cnt_cs <= 0;
ELSE
cnt_cs <= cnt_cs + 1;
END IF;
END IF;
END PROCESS clkdiv;
FSM : PROCESS( clk, clr, state )
BEGIN
IF clr ='0' THEN
cnt_data <= 1;
data <= "11111111";
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN idle =>
IF newcs = '1' THEN
state <= idle;
ELSIF newcs ='0' THEN
state <= adc_r;
END IF;
WHEN adc_r =>
IF cnt_data >0 AND cnt_data <4 THEN
cnt_data <= cnt_data + 1;
state <= adc_r;
ELSIF cnt_data > 3 AND cnt_data <12 THEN
cnt_data <= cnt_data + 1;
data( 11 - cnt_data ) <= dout;
state <= adc_r;
ELSIF cnt_data > 11 AND cnt_data <16 THEN
cnt_data <= cnt_data + 1;
state <= adc_r;
ELSIF cnt_data = 16 THEN
state <= adc_w;
END IF;
WHEN adc_w =>
led <= data;
cnt_data <= 1;
state <= idle;
END CASE;
END IF;
END PROCESS FSM;
END SPI3_BE;



