为什么SRL16不适合成为同步器？

谢谢Eilert！



以下为原文

Thank you Eilert!

T，
SRL16并非设计为同步器。
也就是说，它不一定是坏的，但是可能需要更多的阶段才能使亚稳态事件的概率低于使用同步器指令（以最小延迟最佳地放置DFF）。
用于同步器的两级DFF，具有概率x，通过添加另一级，一个获得x ^ 2。
添加另一个阶段，一个获得x ^ 3（等等）。
也许最佳同步器使用CLB DFF作为第一阶段，然后是快速路径，到SRL16。
有些人认为这比现有的同步器指令解决方案更好，因为您可以添加任意数量的阶段。
但是，Xilinx不支持该解决方案作为同步器（现在Peter Alfke已经通过，测试同步器真的很难！）。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

T,
 
The SRL16 was not designed to be a synchronizer.  That said, it isn't necessarily BAD, but it is likely to take more stages to get the probability of a metastable event lower than using the synchronizer directive (which place DFF optimally with minimum delay).
 
A two stage DFF for a synchronizer, with probability x, by adding another stage, one gets x^2.  Add another stage, one gets x^3 (etc.).
 
Perhaps an optimal synchronizer is using the CLB DFF as the first stage, followed by a fast path, to the SRL16.  Some believe this is even better than the existing synchronizer directive solution, as you may add as many stages as you like.  However, that solution is not supported by Xilinx as a synchronizer (testing synchronizers is really tough now that Peter Alfke has passed!).
Austin Lesea
Principal Engineer
Xilinx San Jose

谢谢奥斯汀。
你能告诉我更多关于同步指令的信息吗？
这是一个像BUFG一样的原始人吗？
或ISE中的配置？
BR，
王天东



以下为原文

Thank you, Austin.
 
Could you please tell more about synchronizer directive? Is it a primitive like BUFG? Or a configuration in ISE?
 
BR,
Tiandong Wang

set_property ASYNC_REG TRUE  [get_cells [list sync0_reg sync1_reg]]
创建一个放置最佳的同步器（在Vivado中）。
只是谷歌'vivado同步器'
Austin Lesea主要工程师Xilinx San Jose



以下为原文

set_property ASYNC_REG TRUE
[get_cells [list sync0_reg sync1_reg]]
 
Creates an optimally placed synchronizer (in Vivado).
 
Just google 'vivado synchronizer'
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose