如何解决用ip核心生成器实现DCM设计错误

我想用ip核心生成器实现DCM，但我无法实现设计。
我有这个错误。
我认为问题出在.ucf档案中。
请帮帮我！
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我的VHDL代码看起来像这样
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entity mainIpcore是Port（CLK_IN1：STD_LOGIC; CLKOUT：out STD_LOGIC; LOCKED：out STD_LOGIC）; end mainIpcore; architectureIpcore的行为是组件DCMIpCoreport（ - 端口CLK_IN1中的时钟：std_logic中的时钟;  - 时钟输出端口CLK_OUT1：out std_logic
;  - 状态和控制信号RESET：in std_logic; LOCKED：out std_logic）; end component; beginmoduloDCM：DCMIpCore port map（ - 端口CLK_IN1 => CLK_IN1， - 时钟输出端口CLK_OUT1 => CLKOUT， - 状态
和控制信号RESET =>'0'，LOCKED => LOCKED）; end Behavioral; -------------------------------
---------------------------------------- UCF achive：
NET“CLK_IN1”LOC = V10;
NET“CLKOUT”LOC = R10;
NET“LOCKED”LOC = U16;
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地方：1205  - 这个设计包含一个全局缓冲实例，驱动网络，驱动以下（前30个）非时钟负载引脚片外。
在Spartan-6中，这种设计实践可能由于全局布线的限制而导致不可预测的情况。
如果设计确实存在路线，则该网络可能存在过度延迟或倾斜。
建议使用时钟转发技术来创建可靠且可重复的低偏斜解决方案：实例化ODDR2组件;
将.D0引脚连接到Logic1;
将.D1引脚连接到Logic0;
将时钟网连接到.C0;
将倒置时钟连接到.C1。
如果您希望覆盖此建议，可以使用.ucf文件中的CLOCK_DEDICATED_ROUTE约束（如下所示）将此消息降级为警告并允许您的设计继续。
虽然网络可能仍未路由，但您可以分析FPGA_Editor中的故障。
错误：包装：1654  - 时序驱动的放置阶段遇到错误。



以下为原文

I want to implement a DCM with the ip core generator but I can't implement the design. I have this error.
I think to the problem is in the .ucf archive.
Help me please!
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My VHDL code looks like this
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entity mainIpcore is
    Port ( CLK_IN1 : in  STD_LOGIC;
           CLKOUT : out  STD_LOGIC;
           LOCKED : out  STD_LOGIC);
end mainIpcore;

architecture Behavioral of mainIpcore is
component DCMIpCore
port
(-- Clock in ports
  CLK_IN1           : in     std_logic;
  -- Clock out ports
  CLK_OUT1          : out    std_logic;
  -- Status and control signals
  RESET             : in     std_logic;
  LOCKED            : out    std_logic
);
end component;
begin

moduloDCM : DCMIpCore
  port map
   (-- Clock in ports
    CLK_IN1 => CLK_IN1,
    -- Clock out ports
    CLK_OUT1 => CLKOUT,
    -- Status and control signals
    RESET  => '0',
    LOCKED => LOCKED);
end Behavioral;
-----------------------------------------------------------------------
The UCF achive:


    NET "CLK_IN1"   LOC =V10;
    NET "CLKOUT"    LOC= R10;
    NET "LOCKED"    LOC= U16;


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Place:1205 - This design contains a global buffer instance,
   , driving the net, , that is driving the
   following (first 30) non-clock load pins off chip.
   < PIN: CLKOUT.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due
   to limitations in the global routing. If the design does route there may be
   excessive delay or skew on this net. It is recommended to use a Clock
   Forwarding technique to create a reliable and repeatable low skew solution:
   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
   Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
   .C1. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue. Although the net
   may still not route, you will be able to analyze the failure in FPGA_Editor.
   < PIN "mERROR:Place:1136 - This design contains a global buffer instance,
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.