嗨，Koike，
您提到的MPN（CYF018V）是一个具有单个DVAL信号的单队列18MEG HDFIFO设备。该设备支持读延迟4。
在您提供的波形中，在启用任用之后，时钟周期1是当HDFIFO将注册第一读取请求时。关于这个时钟边沿，“DVAL 2”在您所提供的波形中，是对设备操作的正确解释。
请告知我们在这方面是否需要进一步澄清。
谢谢和问候，
阿迪西-默西-佩雷普
以上来自于百度翻译
以下为原文
Hi Koike,
The MPN you have mentioned (CYF0018V) is a single queue 18Meg HDFIFO device which has a single DVal signal. The device supports a read latency of 4.
In the waveform you have provided, after REN is enabled, clock cycle 1 is when the HDFIFO will register the first read request. With respect to this clock edge, "DVal#2" in the waveform you have provided, is the correct interpretation of device operation.
Please let us know if any further clarification is required in this regard.
Thanks & Regards,
Adithi Murthy Perepu
嗨，Koike，
您提到的MPN（CYF018V）是一个具有单个DVAL信号的单队列18MEG HDFIFO设备。该设备支持读延迟4。
在您提供的波形中，在启用任用之后，时钟周期1是当HDFIFO将注册第一读取请求时。关于这个时钟边沿，“DVAL 2”在您所提供的波形中，是对设备操作的正确解释。
请告知我们在这方面是否需要进一步澄清。
谢谢和问候，
阿迪西-默西-佩雷普
以上来自于百度翻译
以下为原文
Hi Koike,
The MPN you have mentioned (CYF0018V) is a single queue 18Meg HDFIFO device which has a single DVal signal. The device supports a read latency of 4.
In the waveform you have provided, after REN is enabled, clock cycle 1 is when the HDFIFO will register the first read request. With respect to this clock edge, "DVal#2" in the waveform you have provided, is the correct interpretation of device operation.
Please let us know if any further clarification is required in this regard.
Thanks & Regards,
Adithi Murthy Perepu
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