为什么我这里显示一个警告说输出“hora2”从未使用过？

你好，有人可以帮帮我吗？
我正在尝试制作一个数字时钟。
但是显示一个警告说输出“hora2”从未使用过。
对不起，我的英语不好！
完整代码：https：//www.dropbox.com/sh/8gay1r7bodukjqq/5fGPmj0ZcO
---------------------------
库ieee;使用ieee.std_logic_1164.all;使用ieee.std_logic_arith.all;使用ieee.std_logic_unsigned.all;
实体RelogioDigital isport（clk1：在std_logic; minuto1：out std_logic_vector（3 downto 0）; minuto2：out std_logic_vector（3 downto 0）; hora1：out std_logic_vector（3 downto 0）; hora2：out std_logic_vector（3 downto 0））;
RelogioDigital;
架构RelogioDigital的行为是
signal seg：整数范围0到60：= 0;
信号min1，min2，hr1，hr2：整数范围0到10：= 0;
信号计数：整数：= 1;
开始minuto1 minuto2 hora1 hora2

以上来自于谷歌翻译

以下为原文

Hello, can someone help me?
I'm trying to make a digital clock.
But show one warning saying that the output "hora2" is never used.
Sorry for my bad english !
Complete code: https://www.dropbox.com/sh/8gay1r7bodukjqq/5fGPmj0ZcO
---------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RelogioDigital is
port (clk1 : in std_logic;
minuto1 : out std_logic_vector(3 downto 0);
minuto2 : out std_logic_vector(3 downto 0);
hora1 : out std_logic_vector(3 downto 0);
hora2 : out std_logic_vector(3 downto 0)
);
end RelogioDigital;
architecture Behavioral of RelogioDigital is
signal seg : integer range 0 to 60 :=0;
signal min1,min2,hr1,hr2 : integer range 0 to 10 :=0;
signal count : integer :=1;
begin

minuto1 <= conv_std_logic_vector(min1,4);
minuto2 <= conv_std_logic_vector(min2,4);
hora1 <= conv_std_logic_vector(hr1,4);
hora2 <= conv_std_logic_vector(hr2,4);
process(clk1)
begin
if(clk1'event and clk1='1') then
seg <= seg+ 1;
if(seg = 59) then
seg<=0;
min1 <= min1 + 1;
if(min1 = 9) then
min2 <= min2 + 1;
min1 <= 0;
if(min2 = 5) then
hr1 <= hr1 + 1;
min2 <= 0;
if(hr1 = 3) then
hr1 <= 0;
hr2 <= hr2 + 1;
if(hr2 = 2) then
hr2 <= 0;
end if;
end if;
end if;
end if;
end if;
end if;

end process;
end Behavioral;

------------------------------

杨玲

2019-7-15 15:03:56

你能发布实际的警告信息吗？
输出不是在实体中“使用”，因此如果不使用它，它将指向实例化您发布的实体。
我看了一下你的链接，决定不花太多时间去搜索它。
你可以发布实例化这个实体的代码吗？
此外，当您将代码粘贴到帖子中时，会删除标签，因此我们无法通过正确的缩进来查看它。
因此，要么将标签转换为编辑器中的空格，要么使用“插入代码”功能（撰写帖子时，富文本窗口工具栏中带有“C”的剪贴板）。
- Gabor

以上来自于谷歌翻译

以下为原文

Can you post the actual warning message? Outputs are not "used" within an entity, so if this is not used it would point to the entity that instantiates the one you posted. I took a look at your link and decided not to spend too much time searching for it. Can you post the code for the entity that instantiates this one?

Also when you paste code into a post, tabs are removed, and so we can't see it with proper indenting. So either convert tabs to spaces in your editor, or use the "insert code" feature (clipboard with "C" in the toolbar of the Rich Text window when you compose your post).
-- Gabor

张淑兰

2019-7-15 15:10:07

None

以上来自于谷歌翻译

以下为原文

The problem is that the code is too large
Complete Code Download
Warning:
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
Code:
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity RelogioDigital isport (clk1 : in std_logic;minuto1 : out std_logic_vector(3 downto 0);minuto2 : out std_logic_vector(3 downto 0);hora1 : out std_logic_vector(3 downto 0);hora2 : out std_logic_vector(3 downto 0));end RelogioDigital;architecture Behavioral of RelogioDigital issignal seg : integer range 0 to 60 :=0; signal min1,min2,hr1,hr2 : integer range 0 to 10 :=0; signal count : integer :=1; begin minuto1 <= conv_std_logic_vector(min1,4); minuto2 <= conv_std_logic_vector(min2,4);hora1 <= conv_std_logic_vector(hr1,4);hora2 <= conv_std_logic_vector(hr2,4);process(clk1) beginif(clk1'event and clk1='1') thenseg <= seg+ 1;if(seg = 59) thenseg<=0;min1 <= min1 + 1;if(min1 = 9) thenmin2 <= min2 + 1;min1 <= 0;if(min2 = 5) thenhr1 <= hr1 + 1;min2 <= 0;if(hr1 = 3) thenhr1 <= 0;hr2 <= hr2 + 1;if(hr2 = 2) thenhr2 <= 0;end if;end if;end if;end if;end if;end if;end process;end Behavioral;
Top level code:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity TopLevel isPort( CLOCK : in STD_LOGIC; RESET : in STD_LOGIC ; PAUSE: in STD_LOGIC ; PUSH: in STD_LOGIC; LED: out STD_LOGIC_VECTOR(2 downto 0); DIGITO : out STD_LOGIC_VECTOR (6 downto 0); DISPLAY : out STD_LOGIC_VECTOR (3 downto 0) ) ;end TopLevel;architecture Behavioral of TopLevel is-- Componentes component Decodificador is Port ( clock1: in STD_LOGIC; Entrada1: in STD_LOGIC_VECTOR (3 downto 0); Entrada2: in STD_LOGIC_VECTOR (3 downto 0); Entrada3: in STD_LOGIC_VECTOR (3 downto 0); Entrada4: in STD_LOGIC_VECTOR (3 downto 0); Digito : out STD_LOGIC_VECTOR (6 downto 0); Display : out STD_LOGIC_VECTOR (3 downto 0));end component Decodificador;component DIV1 is Port ( clock_t9 : in STD_LOGIC; --Clock da placa ck_out : out STD_LOGIC); --Clock com frequência divididaend component DIV1;component DIV2 is Port ( clock_t9 : in STD_LOGIC; --Clock da placa ck_out : out STD_LOGIC); --Clock com frequência divididaend component DIV2;component DIV3 is Port ( clock_t9 : in STD_LOGIC; --Clock da placa ck_out : out STD_LOGIC); --Clock com frequência divididaend component DIV3;component TopSel is Port(entrada : in STD_LOGIC;saida : out std_logic_vector(2 downto 0);Clock : in STD_LOGIC);end component TopSel;component Cronometro1 isport (clk1 : in std_logic;auxiliar1 : out std_logic_vector(3 downto 0); auxiliar2 : out std_logic_vector(3 downto 0);auxiliar3 : out std_logic_vector(3 downto 0);auxiliar4 : out std_logic_vector(3 downto 0) ;pause: in std_logic ;reset: in std_logic );end component Cronometro1;component RelogioDigital isport (clk1 : in std_logic;minuto1 : out std_logic_vector(3 downto 0);minuto2 : out std_logic_vector(3 downto 0);hora1 : out std_logic_vector(3 downto 0);hora2 : out std_logic_vector(3 downto 0));end component RelogioDigital;component SeletorSaida is Port ( s : in STD_LOGIC_VECTOR(2 downto 0);-- x = cronômetro 1 x1: in STD_LOGIC_VECTOR (3 downto 0); x2: in STD_LOGIC_VECTOR (3 downto 0); x3: in STD_LOGIC_VECTOR (3 downto 0); x4: in STD_LOGIC_VECTOR (3 downto 0); -- y = relógio y1: in STD_LOGIC_VECTOR (3 downto 0); y2: in STD_LOGIC_VECTOR (3 downto 0); y3: in STD_LOGIC_VECTOR (3 downto 0); y4: in STD_LOGIC_VECTOR (3 downto 0); -- z = cronômetro 2 z1: in STD_LOGIC_VECTOR (3 downto 0); z2: in STD_LOGIC_VECTOR (3 downto 0); z3: in STD_LOGIC_VECTOR (3 downto 0); z4: in STD_LOGIC_VECTOR (3 downto 0); -- saída selecionada saida4 : out STD_LOGIC_VECTOR (3 downto 0) ; saida3 : out STD_LOGIC_VECTOR (3 downto 0) ; saida2 : out STD_LOGIC_VECTOR (3 downto 0) ; saida1 : out STD_LOGIC_VECTOR (3 downto 0)) ;end component SeletorSaida;-- Declaração de Sinaissignal saux1,saux2,saux3,saux4,ss1,ss2,ss3,ss4,out4,out3,out2,out1,scron1,scron2,scron3,scron4: std_logic_vector(3 downto 0);signal sclock1,sclock2,sclock3: std_logic ;signal ssel: std_logic_vector(2 downto 0) ;beginLED <= ssel; -- Mostra nos LEDS o vetor seleção-- ConexõesSelSaida: SeletorSaida PORT MAP ( s => ssel, x1 => saux1, x2 => saux2, x3 => saux3, x4 => saux4, y1 => ss1, y2 => ss2, y3 => ss3, y4 => ss4, z1 => scron1, z2 => scron2, z3 => scron3, z4 => scron4, saida4 => out4, saida3 => out3, saida2 => out2, saida1 => out1);Selecao: TopSel PORT MAP ( entrada => PUSH,saida => ssel,Clock => sclock3 );DivisorCent: DIV1 PORT MAP(clock_t9 => CLOCK,ck_out => sclock1);DivisorSeg: DIV2 PORT MAP(clock_t9 => CLOCK,ck_out => sclock2);DivisorDecod: DIV3 PORT MAP(clock_t9 => CLOCK,ck_out => sclock3);Decod: Decodificador PORT MAP(clock1 => sclock3,Entrada1 => out1,Entrada2 => out2,Entrada3 => out3,Entrada4 => out4,Digito => DIGITO,Display => DISPLAY);CronCent: Cronometro1 PORT MAP (clk1 => sclock1,auxiliar1 => saux1,auxiliar2 => saux2,auxiliar3 => saux3,auxiliar4 => saux4,pause => PAUSE,reset => RESET);CronSeg: Cronometro1 PORT MAP (clk1 => sclock2,auxiliar1 => scron1,auxiliar2 => scron2,auxiliar3 => scron3,auxiliar4 => scron4,pause => PAUSE,reset => RESET);Relogio: RelogioDigital PORT MAP (clk1 => sclock2,minuto1 => ss1, minuto2 => ss2,hora1 => ss3,hora2 => ss4 );end Behavioral;

And "hora" never receives anything!

ProjetoFinal - Cópia.rar ‏1028 KB

None

以上来自于谷歌翻译

以下为原文

The problem is that the code is too large
Complete Code Download
Warning:
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
Code:
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity RelogioDigital isport (clk1 : in std_logic;minuto1 : out std_logic_vector(3 downto 0);minuto2 : out std_logic_vector(3 downto 0);hora1 : out std_logic_vector(3 downto 0);hora2 : out std_logic_vector(3 downto 0));end RelogioDigital;architecture Behavioral of RelogioDigital issignal seg : integer range 0 to 60 :=0; signal min1,min2,hr1,hr2 : integer range 0 to 10 :=0; signal count : integer :=1; begin minuto1 <= conv_std_logic_vector(min1,4); minuto2 <= conv_std_logic_vector(min2,4);hora1 <= conv_std_logic_vector(hr1,4);hora2 <= conv_std_logic_vector(hr2,4);process(clk1) beginif(clk1'event and clk1='1') thenseg <= seg+ 1;if(seg = 59) thenseg<=0;min1 <= min1 + 1;if(min1 = 9) thenmin2 <= min2 + 1;min1 <= 0;if(min2 = 5) thenhr1 <= hr1 + 1;min2 <= 0;if(hr1 = 3) thenhr1 <= 0;hr2 <= hr2 + 1;if(hr2 = 2) thenhr2 <= 0;end if;end if;end if;end if;end if;end if;end process;end Behavioral;
Top level code:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity TopLevel isPort( CLOCK : in STD_LOGIC; RESET : in STD_LOGIC ; PAUSE: in STD_LOGIC ; PUSH: in STD_LOGIC; LED: out STD_LOGIC_VECTOR(2 downto 0); DIGITO : out STD_LOGIC_VECTOR (6 downto 0); DISPLAY : out STD_LOGIC_VECTOR (3 downto 0) ) ;end TopLevel;architecture Behavioral of TopLevel is-- Componentes component Decodificador is Port ( clock1: in STD_LOGIC; Entrada1: in STD_LOGIC_VECTOR (3 downto 0); Entrada2: in STD_LOGIC_VECTOR (3 downto 0); Entrada3: in STD_LOGIC_VECTOR (3 downto 0); Entrada4: in STD_LOGIC_VECTOR (3 downto 0); Digito : out STD_LOGIC_VECTOR (6 downto 0); Display : out STD_LOGIC_VECTOR (3 downto 0));end component Decodificador;component DIV1 is Port ( clock_t9 : in STD_LOGIC; --Clock da placa ck_out : out STD_LOGIC); --Clock com frequência divididaend component DIV1;component DIV2 is Port ( clock_t9 : in STD_LOGIC; --Clock da placa ck_out : out STD_LOGIC); --Clock com frequência divididaend component DIV2;component DIV3 is Port ( clock_t9 : in STD_LOGIC; --Clock da placa ck_out : out STD_LOGIC); --Clock com frequência divididaend component DIV3;component TopSel is Port(entrada : in STD_LOGIC;saida : out std_logic_vector(2 downto 0);Clock : in STD_LOGIC);end component TopSel;component Cronometro1 isport (clk1 : in std_logic;auxiliar1 : out std_logic_vector(3 downto 0); auxiliar2 : out std_logic_vector(3 downto 0);auxiliar3 : out std_logic_vector(3 downto 0);auxiliar4 : out std_logic_vector(3 downto 0) ;pause: in std_logic ;reset: in std_logic );end component Cronometro1;component RelogioDigital isport (clk1 : in std_logic;minuto1 : out std_logic_vector(3 downto 0);minuto2 : out std_logic_vector(3 downto 0);hora1 : out std_logic_vector(3 downto 0);hora2 : out std_logic_vector(3 downto 0));end component RelogioDigital;component SeletorSaida is Port ( s : in STD_LOGIC_VECTOR(2 downto 0);-- x = cronômetro 1 x1: in STD_LOGIC_VECTOR (3 downto 0); x2: in STD_LOGIC_VECTOR (3 downto 0); x3: in STD_LOGIC_VECTOR (3 downto 0); x4: in STD_LOGIC_VECTOR (3 downto 0); -- y = relógio y1: in STD_LOGIC_VECTOR (3 downto 0); y2: in STD_LOGIC_VECTOR (3 downto 0); y3: in STD_LOGIC_VECTOR (3 downto 0); y4: in STD_LOGIC_VECTOR (3 downto 0); -- z = cronômetro 2 z1: in STD_LOGIC_VECTOR (3 downto 0); z2: in STD_LOGIC_VECTOR (3 downto 0); z3: in STD_LOGIC_VECTOR (3 downto 0); z4: in STD_LOGIC_VECTOR (3 downto 0); -- saída selecionada saida4 : out STD_LOGIC_VECTOR (3 downto 0) ; saida3 : out STD_LOGIC_VECTOR (3 downto 0) ; saida2 : out STD_LOGIC_VECTOR (3 downto 0) ; saida1 : out STD_LOGIC_VECTOR (3 downto 0)) ;end component SeletorSaida;-- Declaração de Sinaissignal saux1,saux2,saux3,saux4,ss1,ss2,ss3,ss4,out4,out3,out2,out1,scron1,scron2,scron3,scron4: std_logic_vector(3 downto 0);signal sclock1,sclock2,sclock3: std_logic ;signal ssel: std_logic_vector(2 downto 0) ;beginLED <= ssel; -- Mostra nos LEDS o vetor seleção-- ConexõesSelSaida: SeletorSaida PORT MAP ( s => ssel, x1 => saux1, x2 => saux2, x3 => saux3, x4 => saux4, y1 => ss1, y2 => ss2, y3 => ss3, y4 => ss4, z1 => scron1, z2 => scron2, z3 => scron3, z4 => scron4, saida4 => out4, saida3 => out3, saida2 => out2, saida1 => out1);Selecao: TopSel PORT MAP ( entrada => PUSH,saida => ssel,Clock => sclock3 );DivisorCent: DIV1 PORT MAP(clock_t9 => CLOCK,ck_out => sclock1);DivisorSeg: DIV2 PORT MAP(clock_t9 => CLOCK,ck_out => sclock2);DivisorDecod: DIV3 PORT MAP(clock_t9 => CLOCK,ck_out => sclock3);Decod: Decodificador PORT MAP(clock1 => sclock3,Entrada1 => out1,Entrada2 => out2,Entrada3 => out3,Entrada4 => out4,Digito => DIGITO,Display => DISPLAY);CronCent: Cronometro1 PORT MAP (clk1 => sclock1,auxiliar1 => saux1,auxiliar2 => saux2,auxiliar3 => saux3,auxiliar4 => saux4,pause => PAUSE,reset => RESET);CronSeg: Cronometro1 PORT MAP (clk1 => sclock2,auxiliar1 => scron1,auxiliar2 => scron2,auxiliar3 => scron3,auxiliar4 => scron4,pause => PAUSE,reset => RESET);Relogio: RelogioDigital PORT MAP (clk1 => sclock2,minuto1 => ss1, minuto2 => ss2,hora1 => ss3,hora2 => ss4 );end Behavioral;

And "hora" never receives anything!

ProjetoFinal - Cópia.rar ‏1028 KB

杨玲

2019-7-15 15:29:27

好。
我跟踪信号到“Decodificador”的位置，但我找不到该模块的源代码。
我确实找到了综合报告，但它显示：
警告：Xst：647 - 从不使用输入。
如果该端口属于顶级块或者属于子块并保留该子块的层次结构，则该端口将被保留并保持未连接状态。
Entrada4是未使用信号的目的地。
所以这可以解释为什么不使用它。
您应该仔细检查综合警告，看看哪里有问题。
查看多路复用器模块，看起来您可能也在创建锁存器。
- Gabor

以上来自于谷歌翻译

以下为原文

O.K. I traced the signal to where it goes to "Decodificador" but I couldn't find the source code for that module. I did find the synthesis report, however and it shows:

WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Entrada4 is the destination of the unused signal. So this would explain why it's not used. You should really go through the warnings from synthesis to see where you have problems. Looking at your multiplexer module, it looked like you might also be creating latches.
-- Gabor

王超

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杨玲

张淑兰

杨玲

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