大家好，我有一个斯巴达6 LX150T的问题。
我有一个斯巴达6 150T（未使用MGT）设计，VCCAUX是2.5伏特，大多数I / O是3.3伏特，一个银行使用1.8伏特。
由于启用线路设置为1.8伏特，因此该
电源在接通电源后几百微秒到达。
该存储区与Gums
tix处理器连接，后者控制1.8V稳压器的使能。
Gumstix总线在该银行与以太网控制器共享。
在FGPA配置之后，Gumstix上电精细，以太网正常，1.8伏组上的共享总线上的数据被破坏，导致以太网中的数据包丢失。
即使将该bank上的所有
FPGA引脚设置为输入也会破坏数据。
我也尝试删除所有引脚连接，并使用上拉，拉下和浮动bitgen，但仍然损坏。
Hswapen与gnd绑定，但在配置之后再次没有问题。
我通过禁用1.8volts到银行而不是以太网来验证这一点，然后配置FPGA。
FPGA上的所有其他器件（其他存储体）工作正常，没有数据损坏。
因此，仅仅启动存储区并进行配置会导致数据损坏到连接的总线。
顺便说一句，在重新配置期间，总线完整性恢复正常，直到配置完成，然后再次开始损坏。
我检查过并仔细检查过，银行似乎没有连接针脚。
有什么想法吗？
作者chrisk
以上来自于谷歌翻译
以下为原文
Hello all, I am have a problem with a spartan 6 LX150T.
I have a spartan 6 150T (MGTs are unused) design, VCCAUX is 2.5 volts, most I/O is 3.3Volts, one bank uses 1.8 volts. The power for this bank arrives a few hundred microseconds after power on due to an enable line setting up the 1.8 volts. This bank interfaces to a Gumstix processor which controls the enable to a 1.8 volt regulator. Gumstix bus is shared on this bank with an ethernet controller.
The Gumstix powers up fine, ethernet fine, after FGPA configuration, data is corrupted on the shared bus on the 1.8 volt bank resulting in packet loss in the ethernet. Even setting all FPGA pins on this bank to inputs corrupts the data. I also tried removing all pin connections and used pull up, pull down, and float in bitgen, but still corruption. Hswapen is tied to gnd, but again there are no issues during configuration only after.
I verified this by disabling the 1.8volts to the bank but not to the ethernet, then configuring the FPGA. All other devices on the FPGA (other banks) work fine and no data corruption. So merely powering up the bank and configuring causes data corruption to the attached bus. BTW, during a reconfiguration the bus integrity returns to normal until configuration is complete, then the corruption starts again. I have checked and double checked and there appears to be no pins connected in the bank.
Any thoughts?
Chrisk
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