如何修改占空比以获得10％高和90％低？

如果您使用Xilinx CoreGen工具生成时钟，则可以选择占空比设置
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以下为原文

If you use Xilinx CoreGen tools for clocks generation, then there is option for duty cycle setting
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如果使用DCM生成100MHz时钟，则时钟频率为100MHz的简单逻辑可产生10MHz 10％占空比波形。
- 鲍勃埃尔金德
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以下为原文

If you use the DCM to generate a 100MHz clock, simple logic clocked at 100MHz can generate a 10MHz 10% duty cycle waveform.
 
-- Bob Elkind
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