如何进一步使用以上两个文件查看DSO上的输出？

嗨，
只是一个简短的回复（可能更明天）：
你的主板似乎是Spartan-3E入门套件。
这很重要，因为有更多的板可用于S3E设备。
如果您有不同的电路板，请纠正我。
请查看DAC的数据表。
我非常怀疑SPI接口将以50 MHz的SPI_CLK运行。
因此，虽然FPGA提供固定的50 MHz时钟，但您需要在FPGA内部减少这一点，以使SPI接口正常工作。
您获得的文件需要使用ISE软件进行处理。
您需要运行综合和实现步骤并生成用于配置FPGA的位文件。
这些基本步骤在ISE入门指南中进行了解释。
有一个很好的综合 
Eilert
在原帖中查看解决方案



以下为原文

Hi,
just a short reply (maybe more tomorrow)
:
Your board seems to be the Spartan-3E Starter Kit.
That's important, because there are many more boards available with a S3E Device.
So please correct me if you have a different board.
 
Please take a look at the datasheet of the DAC.
I have a strong doubt that the SPI interface will run with a SPI_CLK of 50 MHz. So, while the FPGA is supplied with the fixed 50 MHz clock, you need to reduce this inside the FPGA to get a working SPI interface up and running.
 
The Files you got need to be processed with the ISE software. You need to run the synthesis and implementation steps and generate a bitfile for configuring the FPGA. These basic steps are explained in teh ISE starter guide.
 
Have a nice synthesis
  Eilert
View solution in original post

嗨，
一些问题：
你有一个UCF文件？
哪个板？
您正在使用clk作为spi_clk。
SPI限制在几百千赫兹（可能是几兆赫兹，但附加设备设置限制），而大多数FPGA板的时钟频率在50到100 MHz之间。
你有另一个减少系统时钟的模块吗？
您正在使用狡猾的方案来序列化分配给“inter”的数据。
但是你有很多总是使用不同时钟信号的块。
模拟没有问题，但合成会有麻烦。
您生成的时钟信号不能放在全局时钟网络上（这在FPGA中也很少见），因此本地路由资源将被用于高偏斜和延迟。
大麻烦！
您应该了解如何使用时钟使能并使用相同的时钟信号触发所有进程。
有一个很好的综合 
Eilert



以下为原文

Hi,
some questions:
You have an UCF file? For which board?
 
You are using the clk as the spi_clk.
SPI is limited to some hundred kilohertz (maybe a few MHz, but the attached device sets the limit) while most FPGA Boards have clocks between 50 and 100 MHz.
Do you have another module that reduces the system clock?
 
You are using a cunning scheme to serialize the data assigned to "inter".
But you have many always blocks wich are using differnt clocking signals.
Simulation has no problem with that, but synthesis will have troubles.
The clock signals that you generate can not be put on global clock nets (which are also very rare in an FPGA), so local routing ressources will be used with high skew and delays. Big trouble!
 
You should learn about how to use clock enables and have all processes triggered with the same clock signal.
 
Have a nice synthesis
  Eilert
 

我为Spartan 3E创建了UCF文件（您可以在附件中看到）。
Spartan 3E的DAC可以支持最高50 MHz（我从用户指南中得到了这一点）。
嗨嘿，我可以知道为什么我应该减少我的系统时钟。
msgstr“”“您应该了解如何使用时钟启用并使用相同的时钟信号触发所有进程。”“”（如果不同进程需要不同的时钟信号，如何使用上述语句?????）
eilert，我能否回答我之前关于“如何使用以上两个文件进一步查看DSO输出”的帖子 
我还有一个问题，我应该在主模块中编写kcpsm3 verilog代码来处理SPARTAN 3E KIT ??? 
提前感谢你:-)
计数器UCF.ucf 1 KB



以下为原文

I have created UCF file  for Spartan 3E (You can see in the attachments) .
The DAC of Spartan 3E can support upto maximum of 50 MHz ( I got this point from User Guide) .
Hi eilert , May i know why i should reduce my system clock.?
"""You should learn about how to use clock enables and have all processes triggered with the same clock signal."""( If different processes need different clock signals how can use the above statement?????)
 
eilert, can i get answer for my previous post regarding "how to proceed further to see the output on DSO using above two files"
         

I have one more question that should i write kcpsm3 verilog code in the main module to work on SPARTAN 3E KIT???

          Thanking you in advance :-)

            Counter UCF.ucf ‏1 KB

嗨，
只是一个简短的回复（可能更明天）：
你的主板似乎是Spartan-3E入门套件。
这很重要，因为有更多的板可用于S3E设备。
如果您有不同的电路板，请纠正我。
请查看DAC的数据表。
我非常怀疑SPI接口将以50 MHz的SPI_CLK运行。
因此，虽然FPGA提供固定的50 MHz时钟，但您需要在FPGA内部减少这一点，以使SPI接口正常工作。
您获得的文件需要使用ISE软件进行处理。
您需要运行综合和实现步骤并生成用于配置FPGA的位文件。
这些基本步骤在ISE入门指南中进行了解释。
有一个很好的综合 
Eilert



以下为原文

Hi,
just a short reply (maybe more tomorrow)
:
Your board seems to be the Spartan-3E Starter Kit.
That's important, because there are many more boards available with a S3E Device.
So please correct me if you have a different board.
 
Please take a look at the datasheet of the DAC.
I have a strong doubt that the SPI interface will run with a SPI_CLK of 50 MHz. So, while the FPGA is supplied with the fixed 50 MHz clock, you need to reduce this inside the FPGA to get a working SPI interface up and running.
 
The Files you got need to be processed with the ISE software. You need to run the synthesis and implementation steps and generate a bitfile for configuring the FPGA. These basic steps are explained in teh ISE starter guide.
 
Have a nice synthesis
  Eilert