为何斯巴达3AN上的TXD / RXD只有四位宽？

亲爱的社区，
我很难添加Xilinx的以太网IP核（核心类型：三模式以太网MAC;版本：4.6）。
除了受到这个核心所需的大量投入和产出的打击之外，我还面临以下基本问题：
我的Spartan 3AN的UCF文件只知道四个TXD和RXD网络：
NET“E_TXD”LOC =“F8”|
IOSTANDARD = LVCMOS33 |
DRIVE = 8 |
SLEW = FAST; NET“E_TXD”LOC =“E7”|
IOSTANDARD = LVCMOS33 |
DRIVE = 8 |
SLEW = FAST; NET“E_TXD”LOC =“E6”|
IOSTANDARD = LVCMOS33 |
DRIVE = 8 |
SLEW = FAST; NET“E_TXD”LOC =“F7”|
IOSTANDARD = LVCMOS33 |
DRIVE = 8 |
SLEW = FAST; NET“E_TX_EN”LOC =“D8”|
IOSTANDARD = LVCMOS33 |
DRIVE = 8 |
SLEW =快;
但核心需要八根线。
我从生成的实例化代码中得出结论：
.emacphytxd（emacphytxd），//输出[7：0] emacphytxd
有没有办法在我的Spartan 3AN上使用这个IP块？
怎么样？
谢谢



以下为原文

Dear community,

I am stuck with adding an ethernet IP core from Xilinx (Core Type: Tri Mode Ethernet MAC; Version: 4.6).


Apart from being struck by the sheer amount of inputs and outputs which are required by this core, I face the following fundamental problem:

my Spartan 3AN's UCF file knows only four TXD and RXD nets:

NET "E_TXD<0>" LOC = "F8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "E_TXD<1>" LOC = "E7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "E_TXD<2>" LOC = "E6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "E_TXD<3>" LOC = "F7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "E_TX_EN" LOC = "D8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

But the core requires eight wires. I conclude this from the generated instantiation code:

.emacphytxd(emacphytxd), // output [7 : 0] emacphytxd

Is there a way to use this IP block with my Spartan 3AN? How?



Thanks