五，
不，他们不会。
由于它们都是不同的频率，因此它们将仅在每个D输入时钟（D =除数，M =乘数）对齐。
由于所有M和D计数器都在每个DCM内，并且不能同时全部复位，因此这些偶然的相位对齐将是巧合（它们将发生，但在每次重置和重新锁定后不可预测）。
我假设您正在使用CLKFX输出，正如您所说的“不同频率”。
如果你没有使用CLKFX，而是使用CLK2X，CLKDV和CLK0（等）输出，那么它们将在某些边沿上全部相位对齐，但该边沿将随每次复位/重新锁定而变化。
我强烈建议您尽可能多地使用一个DCM：它确实有多个输出，并且它们都可以在同一个DCM中同时使用！
我看到设计人员每个时钟使用一个DCM，这既浪费资源又耗电。
Austin Lesea主要工程师Xilinx San Jose
以上来自于谷歌翻译
以下为原文
v,
No, they will not.
Since they are all different frequencies, they will only be phase aligned aligned every D input clocks (D=divisor, M=multiplier). Since all the M and D counters are within each DCM, and can not be all reset at once, these occasional phase alignments will be coincidences (they will happen, but not predictably after each reset and relock).
I am assuming you are using the CLKFX output, as you did say "different frequencies."
If you are not using the CLKFX, but the CLK2X, CLKDV, and CLK0 (etc.) outputs, then again, they will all be phase aligned on some edge, but that edge will vary with each reset/relock.
I strongly suggest you use one DCM as much as possible: it does have a number of outputs, and they may all be used at once from the same DCM! I have seen designers use one DCM per clock, which is a waste of both the resource and the power.
Austin Lesea
Principal Engineer
Xilinx San Jose
五，
不，他们不会。
由于它们都是不同的频率，因此它们将仅在每个D输入时钟（D =除数，M =乘数）对齐。
由于所有M和D计数器都在每个DCM内，并且不能同时全部复位，因此这些偶然的相位对齐将是巧合（它们将发生，但在每次重置和重新锁定后不可预测）。
我假设您正在使用CLKFX输出，正如您所说的“不同频率”。
如果你没有使用CLKFX，而是使用CLK2X，CLKDV和CLK0（等）输出，那么它们将在某些边沿上全部相位对齐，但该边沿将随每次复位/重新锁定而变化。
我强烈建议您尽可能多地使用一个DCM：它确实有多个输出，并且它们都可以在同一个DCM中同时使用！
我看到设计人员每个时钟使用一个DCM，这既浪费资源又耗电。
Austin Lesea主要工程师Xilinx San Jose
以上来自于谷歌翻译
以下为原文
v,
No, they will not.
Since they are all different frequencies, they will only be phase aligned aligned every D input clocks (D=divisor, M=multiplier). Since all the M and D counters are within each DCM, and can not be all reset at once, these occasional phase alignments will be coincidences (they will happen, but not predictably after each reset and relock).
I am assuming you are using the CLKFX output, as you did say "different frequencies."
If you are not using the CLKFX, but the CLK2X, CLKDV, and CLK0 (etc.) outputs, then again, they will all be phase aligned on some edge, but that edge will vary with each reset/relock.
I strongly suggest you use one DCM as much as possible: it does have a number of outputs, and they may all be used at once from the same DCM! I have seen designers use one DCM per clock, which is a waste of both the resource and the power.
Austin Lesea
Principal Engineer
Xilinx San Jose
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