VCO底部，​​中间或顶部是最佳PLL性能吗？

我正在使用Spartan-6 PLL来消除时钟抖动，我在设置VCO频率方面有很大的灵活性（通过操纵M + D值以及DCM馈送PLL的参数）。
UG382，第102页，“目标是使D和M值尽可能小，同时保持f_VCO尽可能高”，这似乎意味着当VCO频率尽可能高但仍然在
数据表参数 - 约1Ghz。
这是真的？
我不是模拟人，但在所有条件相同的情况下，我怀疑电路通常在其规格的外部极限下表现不佳。
如果重要，我只使用PLL进行抖动滤波。



以下为原文

I'm using a Spartan-6 PLL to remove clock jitter, and I have a lot of flexibility in what I set the VCO frequency to (by manipulating the M+D values as well as the parameters on the DCM feeding the PLL).

UG382, page 102, says "the goal is to make D and M values as small as possible while keeping f_VCO as high as possible" which seems to imply that the PLL performs best when the VCO frequency is as high as possible yet still within the datasheet parameters -- around 1Ghz.  Is this true?  I'm not an analog guy, but all things being equal I'd suspect that circuits don't generally perform best at the outer limits of their specifications.

If it matters, I am using the PLL only for jitter filtering.