请问可以使用组合逻辑和serdes选通来获得时序吗？

当从io时钟区域移动到布料时，我对Spartan 6时钟感到有点困惑。
假设您有一个200Mhz的外部时钟，该数据流与用于为iserdes2计时的数据流同步......并且您希望在结构中导出一个门控时钟，用于块存储器写入或数据比较等。核心gen使用bufg缓冲
来自aBUFIO2_2CLK的clk_div。
除了使用更高频率的时钟管理器资源并同步两个频率域之外，是否有一种可接受的方法在结构中使用该bufg用于非时钟输入逻辑？
你可以使用组合逻辑和serdes选通来获得时序吗？



以下为原文

I'm a bit confused on the Spartan 6 clocking when moving from the io clocking region to the fabric.  Say your have a 200Mhz external clock that is synchronus with a data stream being used to clock an iserdes2... and your wanting to derive a gated clock in the fabric for block memory writing or data comparison etc.  Core gen uses a bufg to buffer the clk_div from a BUFIO2_2CLK.  Is there an acceptable method to use that bufg in the fabric for non clock input logic other than use a higher frequency clock manager resource and syncing the two frequency domains?  Can you use combinatorial logic with the serdes strobe to derive timing?