时钟切换通常是一个坏主意。
标准视频输入多路复用器包括
一个短FIFO，用于将输入数据移动到一个公共的“系统”时钟，后跟一个
同步多路复用器。
在您的情况下，如果所有视频都以2个频率之一运行，
但是这些来源都是异步的，你似乎有意义
具有标准的148.5 MHz系统时钟。
如果可以使这个时钟变小
比最快的输入时钟快一点，那么你只需要非常短的FIFO。
除此以外
FIFO深度取决于视频的行长度（假设您只写
有效视频到FIFO）。
在FIFO之后，数据总是伴随着时钟
能够处理数据速率的差异。
输出视频将始终被驱动
通过系统时钟，可能使用74.25 MHz的50％占空比时钟使能
视频类型。
您将再次使用FIFO来确保输出线
由于时钟频率的轻微差异（FIFO欠载）而没有中断。
问候，
的Gabor
- Gabor
以上来自于谷歌翻译
以下为原文
Clock switching is generally a bad idea. The standard video input mux consists of
a short FIFO to move the input data onto a common "system" clock followed by a
synchronous multiplexer. In your case if all video is running at one of 2 frequencies,
but the sources are all asynchronous, it would seem to make sense that you would
have a standard 148.5 MHz system clock. If it is possible to make this clock a tiny
bit faster than the fastest input clock then you need only very short FIFO's. Otherwise
the FIFO depth depends on the line length of the video (presuming you only write
active video to the FIFO). After the FIFO the data is always accompanied by a clock
enable to deal with differences in data rate. Output video would always be driven
by the system clock, possibly using a 50% duty cycle clock enable for the 74.25 MHz
video type. Again you would use a FIFO to make sure that the output lines are
not interrupted due to slight differences in clock frequency (FIFO underrun).
Regards,
Gabor
-- Gabor
时钟切换通常是一个坏主意。
标准视频输入多路复用器包括
一个短FIFO，用于将输入数据移动到一个公共的“系统”时钟，后跟一个
同步多路复用器。
在您的情况下，如果所有视频都以2个频率之一运行，
但是这些来源都是异步的，你似乎有意义
具有标准的148.5 MHz系统时钟。
如果可以使这个时钟变小
比最快的输入时钟快一点，那么你只需要非常短的FIFO。
除此以外
FIFO深度取决于视频的行长度（假设您只写
有效视频到FIFO）。
在FIFO之后，数据总是伴随着时钟
能够处理数据速率的差异。
输出视频将始终被驱动
通过系统时钟，可能使用74.25 MHz的50％占空比时钟使能
视频类型。
您将再次使用FIFO来确保输出线
由于时钟频率的轻微差异（FIFO欠载）而没有中断。
问候，
的Gabor
- Gabor
以上来自于谷歌翻译
以下为原文
Clock switching is generally a bad idea. The standard video input mux consists of
a short FIFO to move the input data onto a common "system" clock followed by a
synchronous multiplexer. In your case if all video is running at one of 2 frequencies,
but the sources are all asynchronous, it would seem to make sense that you would
have a standard 148.5 MHz system clock. If it is possible to make this clock a tiny
bit faster than the fastest input clock then you need only very short FIFO's. Otherwise
the FIFO depth depends on the line length of the video (presuming you only write
active video to the FIFO). After the FIFO the data is always accompanied by a clock
enable to deal with differences in data rate. Output video would always be driven
by the system clock, possibly using a 50% duty cycle clock enable for the 74.25 MHz
video type. Again you would use a FIFO to make sure that the output lines are
not interrupted due to slight differences in clock frequency (FIFO underrun).
Regards,
Gabor
-- Gabor
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