嗨，
你的陈述有点矛盾。
如果您尚未在FPGA上测试/验证IP-Core的功能，为什么还要完成ASIC流程？
如果你的核心没有按预期工作，那么所有的工作都会被浪费掉。
我看到你有一个测试平台。
核心模拟得好吗？
如果您使用ISE进行FPGA流程，只需加载源代码，编写UCF文件以将I / O信号分配给器件引脚即可完成。
但你应该考虑一件事：核心应该如何为自己工作，因为它只是一个界面。
也许您应该添加一些功能来执行与核心的发送和接收操作，以便看到它正常工作。
在虚空中实现这样的接口并不是非常有用。
但是，在提供必要的设置后，只需单击“生成位文件”，流程将自动执行从Synthesis到P＆amp; R的所有步骤。
当一切运行没有错误时，您可以将位文件下载到FPGA并进行测试，无论是什么。
有一个很好的综合
Eilert
以上来自于谷歌翻译
以下为原文
Hi,
your statement is kind of contradicting.
If you haven't tested/verified the function of your IP-Core on an FPGA yet, why have you already completed an ASIC flow?
If your core doesn't work as expected, all the work would be wasted.
I see that you have a testbench. Did the core simulate well?
If you are using ISE for the FPGA flow, just load your sources, write an UCF file to assign the I/O signals to device pins and you are almost done.
But you should think about one thing: How is the core supposed to work for itself, since it's just an interface. Maybe you should add some functionality that performs send and receive operations with the core in order to see it working. Having such an interface implemented in the void isn't very usefull.
However, after you have provided the necessary settings just click on "Generate Bitfile" and the flow will run through all the steps, from Synthesis to P&R automatically. When everything ran without errors, you can download the bitfile to your FPGA and do your testing, whatever that will be.
Have a nice synthesis
Eilert
嗨，
你的陈述有点矛盾。
如果您尚未在FPGA上测试/验证IP-Core的功能，为什么还要完成ASIC流程？
如果你的核心没有按预期工作，那么所有的工作都会被浪费掉。
我看到你有一个测试平台。
核心模拟得好吗？
如果您使用ISE进行FPGA流程，只需加载源代码，编写UCF文件以将I / O信号分配给器件引脚即可完成。
但你应该考虑一件事：核心应该如何为自己工作，因为它只是一个界面。
也许您应该添加一些功能来执行与核心的发送和接收操作，以便看到它正常工作。
在虚空中实现这样的接口并不是非常有用。
但是，在提供必要的设置后，只需单击“生成位文件”，流程将自动执行从Synthesis到P＆amp; R的所有步骤。
当一切运行没有错误时，您可以将位文件下载到FPGA并进行测试，无论是什么。
有一个很好的综合
Eilert
以上来自于谷歌翻译
以下为原文
Hi,
your statement is kind of contradicting.
If you haven't tested/verified the function of your IP-Core on an FPGA yet, why have you already completed an ASIC flow?
If your core doesn't work as expected, all the work would be wasted.
I see that you have a testbench. Did the core simulate well?
If you are using ISE for the FPGA flow, just load your sources, write an UCF file to assign the I/O signals to device pins and you are almost done.
But you should think about one thing: How is the core supposed to work for itself, since it's just an interface. Maybe you should add some functionality that performs send and receive operations with the core in order to see it working. Having such an interface implemented in the void isn't very usefull.
However, after you have provided the necessary settings just click on "Generate Bitfile" and the flow will run through all the steps, from Synthesis to P&R automatically. When everything ran without errors, you can download the bitfile to your FPGA and do your testing, whatever that will be.
Have a nice synthesis
Eilert
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