晶体振荡器漂移的两个最大组件是老化和温度。
我确信电压也在那里，但是次要的。
两个漂移元件都具有非常低的频率特性。
换句话说，漂移很慢。
如果您正在寻找高频抖动，那么它们的最大因素是（并且它们结合并相互作用）：
振荡器输出上升/下降时间与输入缓冲器逻辑阈值对比系统噪声
系统噪声（GND，VCC）将移动逻辑阈值电压（相对于GND）或移动电路板信号电平。
对于单端信号，系统中的噪声意味着接收器（或输入缓冲器）的切换延迟的瞬时变化。
该延迟被夸大到单端信号波形具有慢边缘的程度。
这不是频率变化，而是时钟边沿抖动。
时钟边沿不仅会移动，时钟脉冲宽度（或占空比）也会受到影响。
对这些问题敏感的系统通常使用差分信令或在时钟传播路径的每个阶段使用反相缓冲器。
差分信号消除了共模噪声和逻辑阈值不对称作为误差分量，并有效地使信号边沿速率加倍。
使用反相缓冲级对于两个时钟相位或多或少均匀地分配逻辑阈值不对称性。
你的DRAM定时肚脐凝视项目是怎么来的？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。
以上来自于谷歌翻译
以下为原文
The two largest components for crystal oscillator drift are aging and temperature. I'm sure voltage is in there also, but of secondary importance.
Both drift components have very low frequency characteristics. In other words, drift is slow.
If you're looking for high-frequency jitter, the largest contributing factor to these are (and they combine and interact):
oscillator output rise/fall time vs. input buffer logic threshold vs. system noise
System noise (GND, VCC) will move either logic threshold voltages around (with respect to GND) or move board signal levels around. For a single-ended signal, noise in the system means instantaneous changes in switching delay for receivers (or input buffers). This delay is exaggerated to the extent that the single-ended signal waveform has slow edges.
This isn't a frequency change, it's a clock edge jitter. Not only do the clock edges move around, the clock pulse width (or duty cycle) is also affected. A system which is sensitive to such problems will typically use differential signaling or use inverting buffers at every stage of the clock propagation path.
Differential signaling eliminates common mode noise and logic threshold asymmetry as error components, and effectively double the signal edge rates.
Using inverting buffer stages distributes logic threshold asymmetry more or less evenly for both clock phases.
How's your DRAM timing navel gazing project coming along?
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
晶体振荡器漂移的两个最大组件是老化和温度。
我确信电压也在那里，但是次要的。
两个漂移元件都具有非常低的频率特性。
换句话说，漂移很慢。
如果您正在寻找高频抖动，那么它们的最大因素是（并且它们结合并相互作用）：
振荡器输出上升/下降时间与输入缓冲器逻辑阈值对比系统噪声
系统噪声（GND，VCC）将移动逻辑阈值电压（相对于GND）或移动电路板信号电平。
对于单端信号，系统中的噪声意味着接收器（或输入缓冲器）的切换延迟的瞬时变化。
该延迟被夸大到单端信号波形具有慢边缘的程度。
这不是频率变化，而是时钟边沿抖动。
时钟边沿不仅会移动，时钟脉冲宽度（或占空比）也会受到影响。
对这些问题敏感的系统通常使用差分信令或在时钟传播路径的每个阶段使用反相缓冲器。
差分信号消除了共模噪声和逻辑阈值不对称作为误差分量，并有效地使信号边沿速率加倍。
使用反相缓冲级对于两个时钟相位或多或少均匀地分配逻辑阈值不对称性。
你的DRAM定时肚脐凝视项目是怎么来的？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。
以上来自于谷歌翻译
以下为原文
The two largest components for crystal oscillator drift are aging and temperature. I'm sure voltage is in there also, but of secondary importance.
Both drift components have very low frequency characteristics. In other words, drift is slow.
If you're looking for high-frequency jitter, the largest contributing factor to these are (and they combine and interact):
oscillator output rise/fall time vs. input buffer logic threshold vs. system noise
System noise (GND, VCC) will move either logic threshold voltages around (with respect to GND) or move board signal levels around. For a single-ended signal, noise in the system means instantaneous changes in switching delay for receivers (or input buffers). This delay is exaggerated to the extent that the single-ended signal waveform has slow edges.
This isn't a frequency change, it's a clock edge jitter. Not only do the clock edges move around, the clock pulse width (or duty cycle) is also affected. A system which is sensitive to such problems will typically use differential signaling or use inverting buffers at every stage of the clock propagation path.
Differential signaling eliminates common mode noise and logic threshold asymmetry as error components, and effectively double the signal edge rates.
Using inverting buffer stages distributes logic threshold asymmetry more or less evenly for both clock phases.
How's your DRAM timing navel gazing project coming along?
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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