我试图在XC3S4000-4FG900中为MT8HTF12864HY-667存储器生成两个DDR2控制器。
在MIG 3.0中创建设计时,我保留了引脚,以便控制器使用单独的引脚。
我更新了设计和引脚排列是好的,但对于两个内核,它使用相同的切片进行校准
电路。
例如,用于生成ucf的mig的行读取“INST”Inst_ddr2_2 / infrastructure_top0 / cal_top0 / tap_dly0 / l0“RLOC = X0Y6; INST”Inst_ddr2_2 / infrastructure_top0 / cal_top0 / tap_dly0 / l0“U_SET = delay_calibra
tion_chain;”
当我实例化两个核并组合ucfs时,我在翻译中得到错误,说ucf中存在冲突,因为它们使用相同的切片约束。
有没有人遇到过类似的情况。
任何变通办法。
我不确定在哪里可以安全地移动第二控制器的校准逻辑。
有任何想法吗???
消息编辑由shrutiparashar于07-23-2009 05:50 PM
以上来自于谷歌翻译
以下为原文
I am trying to generate two DDR2 controllers in XC3S4000-4FG900 for MT8HTF12864HY-667 memories. While creating design in MIG 3.0 I reserved pins so that the controllers use separate pins. I updated the designs and pinout is good but for both cores it is using same slices for calibration circuit. For example, a line for mig generated ucf reads "INST "Inst_ddr2_2/infrastructure_top0/cal_top0/tap_dly0/l0" RLOC=X0Y6;
INST "Inst_ddr2_2/infrastructure_top0/cal_top0/tap_dly0/l0" U_SET = delay_calibration_chain;"
When I instantiate both cores and combine ucfs, I get error in translate saying there is a conflict in ucf because they are using same slice constraint.
Has anyone run into similar situation before. Any workarounds. I am not sure where can I safely move 2nd controller's calibration logic to.
Any ideas???
Message Edited by shrutiparashar on 07-23-2009 05:50 PM