void sciaFifoInit(void) {
EALLOW; // Map SCI interrupts to ISR functions
PieVectTable.SCIRXINTA = &sciaRxFifoIsr;
PieVectTable.SCITXINTA = &sciaTxFifoIsr;
EDIS;
SciaRegs.SCICCR.all =0x0007; // 1 Stop bit, no loopback
// no parity, 8 char bits,
// async mode, idle-line protocol
SciaRegs.SCICTL1.all =0x0003; // Enable TX, RX, internal SCICLK,
// disable RX ERR, SLEEP, TXWAKE
SciaRegs.SCICTL2.bit.TXINTENA =1; // Enable Tx interrupt
SciaRegs.SCICTL2.bit.RXBKINTENA =1; // Enable RX interrupt
SciaRegs.SCIHBAUD = 0x0000; // SCI BRR = LSPCLK/(SCI BAUDx8) - 1
SciaRegs.SCILBAUD = 0x00C2; // BRR = (15MHz/(Baud x 8)) - 1. 9600 Baud = 194d = C2h.
SciaRegs.SCIFFTX.all = 0xC022; // Hold SCI in reset, enable FIFO, hold FIFO in reset, clear FIFO status, clear int, enable int, set int level to 0
SciaRegs.SCIFFRX.all = 0x0022; // Clear overflow flag, hold FIFO in reset, clear FIFO status, clear int, enable int, set int level to 3
SciaRegs.SCIFFCT.all = 0x00; // Disable auto-baud feature and set Tx delay to 0
SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
SciaRegs.SCIFFTX.bit.TXFIFOXRESET = 1;
SciaRegs.SCIFFRX.bit.RXFIFORESET = 1;
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, INT1
PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2
IER |= M_INT9;
}
interrupt void sciaRxFifoIsr (void) {
// SCI FIFO interrupt (SCIRXINTA) indicating the SCI FIFO has recieved some data
Uint16 rxBuffer[CNTRL_BUF_LEN];
Uint16 i;
for (i=0; i
rxBuffer[i] = SciaRegs.SCIRXBUF.all; // Read into buffer byte-by-byte
}
sciaTx(0); // Tx response to confirm reciept
SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag
SciaRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag
PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Acknowledge CPU interrupt
}
interrupt void sciaTxFifoIsr(void) {
PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Acknowledge CPU interrupt
}
void sciaFifoInit(void) {
EALLOW; // Map SCI interrupts to ISR functions
PieVectTable.SCIRXINTA = &sciaRxFifoIsr;
PieVectTable.SCITXINTA = &sciaTxFifoIsr;
EDIS;
SciaRegs.SCICCR.all =0x0007; // 1 Stop bit, no loopback
// no parity, 8 char bits,
// async mode, idle-line protocol
SciaRegs.SCICTL1.all =0x0003; // Enable TX, RX, internal SCICLK,
// disable RX ERR, SLEEP, TXWAKE
SciaRegs.SCICTL2.bit.TXINTENA =1; // Enable Tx interrupt
SciaRegs.SCICTL2.bit.RXBKINTENA =1; // Enable RX interrupt
SciaRegs.SCIHBAUD = 0x0000; // SCI BRR = LSPCLK/(SCI BAUDx8) - 1
SciaRegs.SCILBAUD = 0x00C2; // BRR = (15MHz/(Baud x 8)) - 1. 9600 Baud = 194d = C2h.
SciaRegs.SCIFFTX.all = 0xC022; // Hold SCI in reset, enable FIFO, hold FIFO in reset, clear FIFO status, clear int, enable int, set int level to 0
SciaRegs.SCIFFRX.all = 0x0022; // Clear overflow flag, hold FIFO in reset, clear FIFO status, clear int, enable int, set int level to 3
SciaRegs.SCIFFCT.all = 0x00; // Disable auto-baud feature and set Tx delay to 0
SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
SciaRegs.SCIFFTX.bit.TXFIFOXRESET = 1;
SciaRegs.SCIFFRX.bit.RXFIFORESET = 1;
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, INT1
PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2
IER |= M_INT9;
}
interrupt void sciaRxFifoIsr (void) {
// SCI FIFO interrupt (SCIRXINTA) indicating the SCI FIFO has recieved some data
Uint16 rxBuffer[CNTRL_BUF_LEN];
Uint16 i;
for (i=0; i
rxBuffer[i] = SciaRegs.SCIRXBUF.all; // Read into buffer byte-by-byte
}
sciaTx(0); // Tx response to confirm reciept
SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag
SciaRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag
PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Acknowledge CPU interrupt
}
interrupt void sciaTxFifoIsr(void) {
PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Acknowledge CPU interrupt
}
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