DSPIC板不能让PLL工作

你好，我有一个DSPIC板，不能让PLL工作。我对水晶很怀疑，所以我需要澄清我的代码没有任何问题。我的代码有问题吗？？



      以下为原文

    Hello,

I have a board with that dspic and could not make pll work. I am suspicious about the crystal so i need to clarify that my code has not any problem.

Is there any problem with my code??

#pragma config ICS = PGD2 // ICD Communication Channel Select bits (Communicate on PGEC2 and PGED2)
#pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)

// FPOR
#pragma config ALTI2C1 = ON // Alternate I2C1 pins (I2C1 mapped to ASDA1/ASCL1 pins)
#pragma config ALTI2C2 = ON // Alternate I2C2 pins (I2C2 mapped to ASDA2/ASCL2 pins)
#pragma config WDTWIN = WIN75 // Watchdog Window Select bits (WDT Window is 75% of WDT period)

// FWDT
#pragma config WDTPOST = PS32768 // Watchdog Timer Postscaler bits (1:32,768)
#pragma config WDTPRE = PR128 // Watchdog Timer Prescaler bit (1:128)
#pragma config PLLKEN = OFF // PLL Lock Enable bit (Clock switch will not wait for the PLL lock signal.)
#pragma config WINDIS = OFF // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)
#pragma config FWDTEN = OFF // Watchdog Timer Enable bit (Watchdog timer enabled/disabled by user software)

// FOSC
#pragma config POSCMD = NONE // Primary Oscillator Mode Select bits (Primary Oscillator disabled)
#pragma config OSCIOFNC = OFF // OSC2 Pin Function bit (OSC2 is clock output)
#pragma config IOL1WAY = OFF // Peripheral pin select configuration (Allow multiple reconfigurations)
#pragma config FCKSM = CSDCMD // Clock Switching Mode bits (Both Clock switching and Fail-safe Clock Monitor are disabled)

// FOSCSEL
#pragma config FNOSC = FRC // Oscillator Source Selection (Internal Fast RC (FRC))
#pragma config PWMLOCK = ON // PWM Lock Enable bit (Certain PWM registers may only be written after key sequence)
#pragma config IESO = ON // Two-speed Oscillator Start-up Enable bit (Start up device with FRC, then switch to user-selected oscillator source)

// FGS
#pragma config GWRP = OFF // General Segment Write-Protect bit (General Segment may be written)
#pragma config GCP = OFF // General Segment Code-Protect bit (General Segment Code protect is Disabled)

#include
#include "common.h"

/*
                         Main application
*/
int main(void)
{
    // Configure PLL prescaler, PLL postscaler, PLL divisor
    PLLFBD=46; // M=48
    CLKDIVbits.PLLPOST=0; // N2=2
    CLKDIVbits.PLLPRE=0; // N1=2
    // Initiate Clock Switch to Primary Oscillator with PLL (NOSC=0b011)
    __builtin_write_OSCCONH(0x03);
    __builtin_write_OSCCONL(OSCCON | 0x01);
    // Wait for Clock switch to occur
    while (OSCCONbits.COSC!= 0b011);
    // Wait for PLL to lock
    while (OSCCONbits.LOCK!= 1);

    TRISAbits.TRISA7 = OUTPUT;
    TRISAbits.TRISA10 = OUTPUT;
    while (1)
    {
        __delay_ms(500);
        LATAbits.LATA10 = 1;
        LATAbits.LATA7 = 1;
        __delay_ms(500);
        LATAbits.LATA10 = 0;
        LATAbits.LATA7 = 0;
        // Add your application code
    }
}

/*common.h*/
    #define FCY 60000000UL

#define OUTPUT 1
#define INPUT 0

    #define MapLock() __builtin_write_OSCCONL(OSCCON | (1<<6))
#define MapUnLock() __builtin_write_OSCCONL(OSCCON & ~(1<<6))