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侯晓萃

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[问答]

FX2以EP Full标志怎么设置开始

在重命名之后,FX2通常从EXXCS寄存器中声明的完整标志开始,尽管通常集合了F断言断言。
EPA2的NPAK状态为010,EP4为10。其他我不感兴趣的。
尽管EpxFIFBCL寄存器正确地报告了0个字节,这种情况还是发生了。
从冷启动,这不会发生。
无论如何,在重新命名之后,是否强制撤销完整标志?
假设这个完整的标志是为什么我不能将数据发送到主机的端点(timeOutter),那么我也是正确的吗?

以上来自于百度翻译


     以下为原文
   After a renumeration, the FX2 often starts with the FULL flags asserted in the EPxCS registers, despite the usual collection of FIFORESET assertions.
    NPAK status for EP2 is 010, and for EP4 10. The others I am not interested in.
    This happens, despite the EPxFIFOBCL registers correctly reporting 0 bytes.
    From a cold boot, this does not occur.
    Is there anyway to force the FULL flag to be deasserted after renumeration?
    Am I also correct in assuming that this FULL flag is why I am unable to send data to the endpoints from the host (timeout instead)?

回帖(11)

何柳青

2019-3-20 12:48:48
嗨,Ali,
使用的端点配置是什么,端点使用和它们的缓冲。很可能你并没有正确地配置它们。另一件事是,你是通过在VFET序列之后写0x80到EXBCL寄存器来终结端点。
问候,阿南德

以上来自于百度翻译


     以下为原文
  Hi Ali,
    What is the endpoint configuration you're using,
Endpoints used and their buffering. Most probably you're not configuring them right. One other thing is, are you arming OUT endpoints by writing 0x80 to the EPxBCL register after the FIFORESET sequence.
    Regards,
Anand
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侯晓萃

2019-3-20 13:00:13
设置端点的初始化代码:
无效的用户()
{
EA=0;/ /中断禁用-简化调试和设置时间
IFCONFIG=0xE3;SycDelayle();//内部,48 MHz,同步,从
ReVCTL= 0x03;SycDelay.();
//设置调试端点
EP1OutCFG= 0xB0;SycDelay.();/ /中断
EP1CIFFG=0xB0;SycDelay.();
ReARMEP1();
/init标志。在DOCS/FPGA-CyPACTET.TXT中列出
pFrAGSABA= 0x8C;SycDelay.();
pFrAgCSCD= 0x09;SycDelay.();
//FIFONIOLID= 0x00;SycDelay.();
//设置LED输出,并照亮它
PTCCFG&AMP= ~0x80;
OEC=0x80;
SycDelay.();
PC7=1;
/整理FIFO
//参阅:HTTP//www-RelabalCalp/Cu/EnEnt/Engut/St/6142-2-1.PHP
/CyPress芯片和“全”旗在暖启动时发出
EP2CFG=0xE4;SycDelay.();
EP4CFG=0xA2;SycDelay.();
EP6CFG= 0x00;SycDelay.();
EP8CFG=0x00;SycDelay.();
FiPosie= 0x80;SycDelay.();
FiPosit=0x82.;
FiPosit=0x84. SycDelay.();
FiPosit=0x86.
FiPosit=0x88;SycDelay.();
FiPosie= 0x00;SycDelay.();
OutpkStay= 0x84. SycDelay.();
OutpkStay= 0x84. SycDelay.();
IpkChans= 0x82.;
IpkChans= 0x82.;
EP2FIFOCFG=0x00;SycDelayy(;)/ /以确保它看到0和1的过渡。
EP4FIFOCFG=0x00;SycDelay.();
EP2FIFOCFG=0x0b;SycDelay.();
EP4FIFOCFG=0x11;SycDelay.();
EP2AutoLunh=0x01;SycDelay.();
EP2AutoLeNLL=0x00;SycDelay.();
EA=1;
}

以上来自于百度翻译


     以下为原文
   My initialisation code for setting endpoints:
     
    void init_user()
    {
  EA = 0; //Interrupts disabled - simplify debugging and setup times
 
  IFCONFIG = 0xE3; SYNCDELAY(); //internal, 48MHz, SYNC, slave
  REVCTL = 0x03; SYNCDELAY();
 
  //Setup debug endpoints
  EP1OUTCFG = 0xB0; SYNCDELAY(); //Interrupt
  EP1INCFG = 0xB0; SYNCDELAY(); 
  REARMEP1OUT();
 
   //init flags. listed in docs/fpga-cypacket.txt
  PINFLAGSAB = 0x8C; SYNCDELAY();
  PINFLAGSCD = 0x09; SYNCDELAY();
  //FIFOINPOLAR = 0x00; SYNCDELAY();
 
  //Setup LED output, and light it
  PORTCCFG &= ~0x80;
  OEC |= 0x80;
  SYNCDELAY();
  PC7 = 1;
 
  //Sort out FIFOs
  //see: http://www.embeddedrelated.com/usenet/embedded/show/65142-1.php
  //Issue with cypress chip and 'full' flag on a warm start
  EP2CFG = 0xE4; SYNCDELAY();
  EP4CFG = 0xA2; SYNCDELAY();
  EP6CFG = 0x00; SYNCDELAY();
  EP8CFG = 0x00; SYNCDELAY();
 
  FIFORESET = 0x80; SYNCDELAY();
  FIFORESET = 0x82; SYNCDELAY();
  FIFORESET = 0x84; SYNCDELAY();
  FIFORESET = 0x86; SYNCDELAY();
  FIFORESET = 0x88; SYNCDELAY();
  FIFORESET = 0x00; SYNCDELAY();
 
  OUTPKTEND = 0x84; SYNCDELAY();
  OUTPKTEND = 0x84; SYNCDELAY();
  INPKTEND = 0x82; SYNCDELAY();
  INPKTEND = 0x82; SYNCDELAY();
 
  EP2FIFOCFG = 0x00; SYNCDELAY(); //to ensure it sees a 0->1 transition
  EP4FIFOCFG = 0x00; SYNCDELAY();
 
  EP2FIFOCFG = 0x0B; SYNCDELAY();
  EP4FIFOCFG = 0x11; SYNCDELAY();
 
  EP2AUTOINLENH = 0x01; SYNCDELAY();
  EP2AUTOINLENL = 0x00; SYNCDELAY();
 
  EA = 1;
}
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何柳青

2019-3-20 13:10:50
Ali
您正在使用一个无效的端点配置。请查看12个有效端点配置的最新TRM的第30页。此外,如果不使用端点,不要写入其EXCFCFG寄存器来禁用它。如果未使用端点,则应避免向与其对应的寄存器写入。
EP2CFG=0xE4????这个说法似乎也是错误的。
问候,阿南德

以上来自于百度翻译


     以下为原文
  Ali,
    You're using an invalid endpoint configuration. Please look at page 30 of the latest TRM for the 12 valid endpoint configurations. Also if you're not using a endpoint do not write to its EPxCFG register to disable it. If an endpoint is not being used you should avoid writing to registers corresponding to it.
    EP2CFG = 0xE4???? This statement also seems wrong.
    Regards,
Anand
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侯晓萃

2019-3-20 13:20:32
对不起,我本应该发现的。我已经把它改为使用11型(EP2 1024×3 +EP8 512×2):
FB;SycDelay[();Ep6CFG= 0x00;SycDelay-();Ep8CFG= 0xA0;SycDelay.(;FiPosie= 0x80;SycDelay.);FippeTe= 0x82.;SycDelay.(;)FiPosie= 0x84.;SycDelay.(;),FippeTe= 0x86;SycDelay.(;)EP2CFG=0XX88;SycDelay-();OpkkTale= 0x82.;SycDelay-(;);PkkTale= 0x82.;SycDelay-(;);PykTyrase= 0x82.;SycDelay.(;)EP2FIFOFFG=0x00;SycDelayy(;)/ /以确保它看到一个0和1的过渡EP8FIFOCFG=0x00;SycDelaye();EP2FIFOCFG=0x0b;SycDelay.();EP8FIFOFFG;UTPKTACEE= 0= 0x11;SycDelay-();EP2AutoLunh=0x01;SycDelayle();EP2AutoLunl=0x00;SycDelay-();EP不再看起来标记为“满”,但我仍然无法与FX2通信。在发送2个包(填充缓冲区)之后,我得到超时,并且在2次读取尝试之后(我想它应该在3次缓冲之后),我得到超时。还有什么意见吗?

以上来自于百度翻译


     以下为原文
   Sorry, I should have spotted that. I have changed it to use type 11 (EP2 1024*3 + EP8 512*2):
      EP2CFG = 0xFB; SYNCDELAY();   EP4CFG = 0x00; SYNCDELAY();   EP6CFG = 0x00; SYNCDELAY();   EP8CFG = 0xA0; SYNCDELAY();    FIFORESET = 0x80; SYNCDELAY();   FIFORESET = 0x82; SYNCDELAY();   FIFORESET = 0x84; SYNCDELAY();   FIFORESET = 0x86; SYNCDELAY();   FIFORESET = 0x88; SYNCDELAY();   FIFORESET = 0x00; SYNCDELAY();    OUTPKTEND = 0x88; SYNCDELAY();   OUTPKTEND = 0x88; SYNCDELAY();   INPKTEND = 0x82; SYNCDELAY();   INPKTEND = 0x82; SYNCDELAY();   INPKTEND = 0x82; SYNCDELAY();    EP2FIFOCFG = 0x00; SYNCDELAY(); //to ensure it sees a 0->1 transition   EP8FIFOCFG = 0x00; SYNCDELAY();    EP2FIFOCFG = 0x0B; SYNCDELAY();   EP8FIFOCFG = 0x11; SYNCDELAY();    EP2AUTOINLENH = 0x01; SYNCDELAY();   EP2AUTOINLENL = 0x00; SYNCDELAY();  The EP's no longer seem to be coming up marked as full anymore, but I am still unable to communicate with the FX2). After sending 2 packets (which fills the buffer), I get timeouts, and after 2 read attempts (I would have thought it should be after 3 since triple buffering), I get timeouts. Any more comments?   
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