Cypress技术论坛
直播中

李丽波

8年用户 207经验值
私信 关注
[问答]

怎么在两个高速ISO端点上流式传输

您好!
我想有两个高速ISO端点流(pkt_size = 3×1024)双缓冲。我写了一个固件使用autoin模式和从属FIFO和它的工作罚款外主(FPGA)当我用包大小2048(= 2×1024)。通过使用赛普拉斯尖叫有一些修改,接收数据速率达到31.8 Mbps。
但是当我使用的数据包大小为3072,达成率48 Mbps的端点,ISO传输失败(使用cyconsole)。
有人已经成功的将采用两高速ISO端点?
有什么建议吗?
附加信息:
我使用2010个CYUSB驱动程序。
我用Keil uVision4 FW和Visual Studio 2010(VC #)应用程序。
提前感谢

以上来自于百度翻译


     以下为原文
  Hi
    I want to have streaming on two highspeed ISO endpoints (pkt_size= 3 * 1024) with double buffering. I wrote a firmware using AUTOIN mode and slave fifo and it worked fine with external master (FPGA) when i used packet size 2048(=2*1024). By use of Cypress Screamer with a few modifications, rate of receiving data reaches 31.8 MBps.
    but when I use packet size 3072 for endpoints for achieving rate 48 MBps, the ISO transfer failed (using CyConsole).
    Is there anybody that has successful transfers using two highspeed ISO endpoints?
    Any suggesstion?
    Additional information:
    I use 2010 CyUSB driver.
    I use keil uvision4 for FW and visual studio 2010 (VC#) for APP.
    Thank you in advance

回帖(2)

李丽波

2019-3-14 16:49:44
又喜
几天前,我用FX2内的8051创建了包,并在工作中使用。转移率达到48 Mbps。
我认为原因是,他们得到的数据从60 Mbps速率FIFO和我写FIFO 48 Mbps。所以我不能及时填写FIFO。当我使用高速ISO端点每微帧和双缓冲三包,很明显,传输失败。
我想是没有办法用FX2与两高速ISO EPS分别为双缓冲。
如果你对此有什么意见,请告诉我。

以上来自于百度翻译


     以下为原文
  Hi again
     
    Some days ago, I created packets using 8051 inside FX2 and in worked. Transfer rate reached 48 MBps.
    I think the reason is that, SIE gets data from fifo with rate of 60 MBps and I write to fifo with 48 MBps. So I can not fill fifo in time. When I use High-Speed ISO endpoint with 3 packets per microframe and double buffering, it is obvious that transmission fails.
    I think there is no way to use FX2 with two High-Speed ISO EPs with double buffering for each of them.
    If you have any opinion about it, let me know please.
举报

何柳青

2019-3-14 17:02:53
60MbPS是理论速度。当你说48兆赫,你假设时钟在一个字节在每个时钟周期上的GPIF /从FIFO。如果使用所有16条数据线,FX2LP每时钟周期最多可以达到2字节。即92MbPs大于USB协议所能提供的。因此,FX2LP能够提供您的速度要求。
当做,
阿南德

以上来自于百度翻译


     以下为原文
  60MBps is the theoretical speed. When you say 48MHz you are assuming clocking in a byte every clock cycle on the GPIF/Slave FIFO. FX2LP can go upto 2bytes per clock cycle if you use all 16 data lines. i.e. 92MBps which is greater than what USB protocol can offer. so FX2LP is capable of offering your speed requirement.
    Regards,
    Anand
举报

更多回帖

发帖
×
20
完善资料,
赚取积分