您好，我在研发过程中，使用AD9963芯片，在XILINX的EDK开发工具中利用SDK对其进行配置，配置情况如下：
* Default AD9963 configuration:
-Full-duplex mode (Tx data on TXD port, Rx data on TRXD port)
-Power up everything except:
-DAC12A, DAC12B, AUXADC (all unconnected on PCB)
-DLL
-Clocking:
-DLL disabled
-ADC clock = DAC clock = ext clock (nominally 80MHz)
-Tx path:
-Data in 2's complement (NOTE: datasheet bug!)
-TXCLK is input at TXD sample rate
-TXD is DDR, I/Q interleaved, I first
-Tx interpolation filters bypassed
-Tx gains:
-Linear gain set to 100%
-Linear-in-dB gain set to -3dB
-DAC RSET set to 100%
-Tx DCO DACs:
-Enabled, configured for [0,+2]v range
-Set to mid-scale output (approx equal to common mode voltage of I/Q diff pairs)
-Rx path:
-TRXCLK is output at TRXD sample rate
-TRXD is DDR, I/Q interleaved, I first
-Decimation filter bypassed
-RXCML output enabled (used by ADC driver diff amp)
-ADC common mode buffer off (required for DC coupled inputs)
-Rx I path negated digitally (to match swap of p/n traces on PCB)
*/
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