Ciao Jerry，
我想请你澄清一下RTS信号。
我已经使用套接字实现了我的数据传输。数据以4 kByte块分割，并与AT + S.SOCKW命令序列一起发送。一切都很好。
我看到的是，在每个4 KB的传输过程中，RTS信号每1024字节升高~3.5 ms。即使我完全忽略它，也可以正确获取所有数据。 UART速度是默认的115200波特。
我想知道我是否可以放心地忽略这个RTS故障。如果忽略它不会造成伤害，我无法理解它的目的。
我的猜测是，一旦UART完成第1024字节接收，内部1 kByte缓冲区就满了，RTS被置位（取消断言），数据从第一个字节开始从其他地方的内部缓冲区（另一个内部缓冲区？）传输。内部传输的速度是这样的，当UART获得第1025个字节（之后约87μs）时，缓冲区的第一个字节已经被释放，因此可以安全地存储传入的新字节。然后最终，当原始的前1024个字节已被传输（之后约3.5毫秒）时，RTS再次被置位。
我对吗？我可以假设这种行为是一致的，所以如果UART速度不是太高，RTS信号可以被忽略吗？
这对我来说非常重要，因为我的MCU是5V供电而RTS信号高电平（2.5 V）太低而没有电平转换。它是一个5V耐压引脚，当上拉时它不使用时会上升到5V，但是当它工作时它会从0V上升到2.5V。糟糕的是它不是一个开路集电极（对于TX引脚也是如此：5V容忍但是推挽，因此需要额外的电路）。如果我可以放心地忽略它，那就更好了。
谢谢。
卢卡
以上来自于谷歌翻译
以下为原文
Ciao Jerry,
I'd like to ask you a clarification about the RTS signal.
I've implemented the transmission of my data using a socket. The data is split in 4 kByte chunks and sent with a sequence of AT+S.SOCKW commands. Everything is working fine.
What I see is that during each 4 KByte transmission the RTS signal is raised every 1024 bytes for ~3.5 ms. Even if I completely ignore it, all data is correctly acquired. The UART speed is the default 115200 baud.
I'd like to know if I can safely ignore this RTS glitch. I can't understand its purpose if ignoring it causes no harm.
My guess is that as soon as the UART completes the 1024th byte reception the internal 1 kByte buffer is full, RTS is raised (deasserted) and the data is transferred from the internal buffer somewhere else (another internal buffer?) starting from the first byte. The speed of the internal transfer is such that when the UART gets the 1025th byte (~87 µs after), the first bytes of the buffer have already been freed so the incoming new bytes can be safely stored. Then eventually, when the original first 1024 bytes have been transferred (~3.5 ms after), the RTS is asserted again.
Am I right? Can I assume this behavior is going to be consistent so if the UART speed is not too high the RTS signal can be ignored?
This is an important point for me because my MCU is powered at 5V and the RTS signal high level (2.5 V) is too low to be seen without a level shift. It's a 5V tolerant pin such that with a pull-up it goes up to 5V when it's not in use, but when it's working it goes from 0V to 2.5V. Bad it's not an open collector (and the same is true for the TX pin: 5V tolerant but push-pull so additional circuitry is needed). If I can safely ignore it, it would be better.
Thank you.
Luca
Ciao Jerry，
我想请你澄清一下RTS信号。
我已经使用套接字实现了我的数据传输。数据以4 kByte块分割，并与AT + S.SOCKW命令序列一起发送。一切都很好。
我看到的是，在每个4 KB的传输过程中，RTS信号每1024字节升高~3.5 ms。即使我完全忽略它，也可以正确获取所有数据。 UART速度是默认的115200波特。
我想知道我是否可以放心地忽略这个RTS故障。如果忽略它不会造成伤害，我无法理解它的目的。
我的猜测是，一旦UART完成第1024字节接收，内部1 kByte缓冲区就满了，RTS被置位（取消断言），数据从第一个字节开始从其他地方的内部缓冲区（另一个内部缓冲区？）传输。内部传输的速度是这样的，当UART获得第1025个字节（之后约87μs）时，缓冲区的第一个字节已经被释放，因此可以安全地存储传入的新字节。然后最终，当原始的前1024个字节已被传输（之后约3.5毫秒）时，RTS再次被置位。
我对吗？我可以假设这种行为是一致的，所以如果UART速度不是太高，RTS信号可以被忽略吗？
这对我来说非常重要，因为我的MCU是5V供电而RTS信号高电平（2.5 V）太低而没有电平转换。它是一个5V耐压引脚，当上拉时它不使用时会上升到5V，但是当它工作时它会从0V上升到2.5V。糟糕的是它不是一个开路集电极（对于TX引脚也是如此：5V容忍但是推挽，因此需要额外的电路）。如果我可以放心地忽略它，那就更好了。
谢谢。
卢卡
以上来自于谷歌翻译
以下为原文
Ciao Jerry,
I'd like to ask you a clarification about the RTS signal.
I've implemented the transmission of my data using a socket. The data is split in 4 kByte chunks and sent with a sequence of AT+S.SOCKW commands. Everything is working fine.
What I see is that during each 4 KByte transmission the RTS signal is raised every 1024 bytes for ~3.5 ms. Even if I completely ignore it, all data is correctly acquired. The UART speed is the default 115200 baud.
I'd like to know if I can safely ignore this RTS glitch. I can't understand its purpose if ignoring it causes no harm.
My guess is that as soon as the UART completes the 1024th byte reception the internal 1 kByte buffer is full, RTS is raised (deasserted) and the data is transferred from the internal buffer somewhere else (another internal buffer?) starting from the first byte. The speed of the internal transfer is such that when the UART gets the 1025th byte (~87 µs after), the first bytes of the buffer have already been freed so the incoming new bytes can be safely stored. Then eventually, when the original first 1024 bytes have been transferred (~3.5 ms after), the RTS is asserted again.
Am I right? Can I assume this behavior is going to be consistent so if the UART speed is not too high the RTS signal can be ignored?
This is an important point for me because my MCU is powered at 5V and the RTS signal high level (2.5 V) is too low to be seen without a level shift. It's a 5V tolerant pin such that with a pull-up it goes up to 5V when it's not in use, but when it's working it goes from 0V to 2.5V. Bad it's not an open collector (and the same is true for the TX pin: 5V tolerant but push-pull so additional circuitry is needed). If I can safely ignore it, it would be better.
Thank you.
Luca
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