你好，
您似乎正在调用内部“写锁存器”，每当写入发生时，它会被设置为脏位。这意味着您希望写入SRAM，但不希望在HSB/AISH声明时存储写入数据。如果这是你想要的，你有什么理由不能离开HSB/OPEN？
另外，为什么应用程序在每次上电时禁用AutoSt店。你可以做一次，做一个SW商店，让它承受功率循环。然后，只有当你做软件商店（HSW商店，如果HSB被断言当发生了写）时，商店才会发生。
我已经把我的答案放在你的问题中了。
问：CY14B256LA的数据表提到了20年的数据保持。其他NVSRAM产品列出100年。这是最近20年的存储操作，还是20年的芯片寿命？
在CY14B256LA中的20年数据保持在85℃下保证。在旧技术部分（0.8U部分）中的100年保证在5C。如果在相同的温度下进行比较，新部件有4倍于旧部件的数据保留。我们已经在App Note AN55 662中声明了这一点。
数据保留超过了部件的寿命。20年是积累的数据保留时间。
问：有没有办法从芯片上读取选项状态？
如果AutoStore被禁用了，那么禁用它再作为一个写入，就如同芯片的寿命一样吗？例如，如果包含芯片的设备在每次打开时自动禁用AutoStury，那么每个禁用的操作会通过占用1000000个存储计数来导致“耗尽”芯片吗？
不幸的是，无法检查一部分中的AutoStutial/Atdiable状态。
禁止存储不算作写入，也不影响1M存储计数。
AutoSturyAsabor或禁用是通过特定的读取顺序完成的。没有涉及写入周期。
读/写周期是对NVSRAM的SRAM部分进行的。SRAM具有无限的读/写持久性。
只有储存周期才算耐力。由于您禁用了AutoSt店，所以当您想将数据保存到NVSRAM的NV部分时，假设您将执行软件商店或硬件商店。只有那些商店才算耐用。
问：
禁用AutoSt店设置芯片的“脏位”，从而导致当/HSB被断言时存储吗？
正如前面所讨论的，在执行读取时，不设置写入锁存器。我认为你正在考虑内部写锁存为“肮脏的比特”，虽然我不明白为什么你这样认为。内部写锁存器在没有写入时防止不必要的存储（因此内容不改变）。我假设当HSB/AS被断言时，您不希望存储发生。如果是这样，如果您只执行读取，存储不会发生。但是，如果您已经完成了写入操作，并且不希望存储数据，则需要确保HSB/IS不被断言。或者，你可以离开HSB/OPEN。
如果设置了脏位，则当/HSB被断言时存储的所有字节，还是只有SRAM值与其存储值不同的字节？“
当存储发生时，它将发生在所有字节上。存储过程包括擦除完整的NV存储器并将完整的SRAM内容存储到NV存储器中。
Ravi，NVSRAMAPP经理
以上来自于百度翻译
以下为原文
Hi,
You seem to be calling the internal "write latch" which gets set whenever a write happens, as dirty bit. Which implies that you want to write into the SRAM but you do not want the written data to be Stored when HSB/ is asserted. If this is what you desire, is there any reason you cannot leave the HSB/ open?
Also, why is the application disabling AutoStore at every power up. You can do it once and do a SW store to make it endure power cycles. Fom then on, Stores will happen only when you do a software Store (HW store if HSB is asserted when write has happened).
I have placed my answers to your questions inline marked
##.
Q: The datasheet for the CY14B256LA mentions 20-year data retention. Other nvSRAM products list 100 years. Is that 20 years from the most recent store operation, or 20 years total over the life of the chip?
## The 20 year data retention in the CY14B256LA is guaranteed at 85C. The 100 years in the old technology part (0.8u parts) is guaranteed at 55C. If comparison is made at the same temperatures, the new parts have 4 times the data retention of the older part.. We have stated this in the app note AN55662.
## The data retention is over the life of the part. 20 years is the accumulated data retention time.
Q: Is there any way of reading the option status from the chip?
If AutoStore is disabled, does disabling it again count as a write as far as the life of the chip goes? For example, if the device containing the chip automatically disables AutoStore every time it turns on, does each disable operation contribute to "wearing out" the chip by eating into the 1,000,000 store count?
## Unfortunately there is no way to check the enable/disable status of AutoStore in a part.
## AutoStore disabling does not count as a write nor does it affect the 1M store count.
- Autostore anable or disable is done through a specific sequence of reads. There is no write cycle involved.
- Read/write cycles are done to the SRAM portion of the nvSRAM. The SRAM has infinite read/write endurance.
- Only Store cycles count for endurance. Since you are disabling autostore, I assume you will be performing a software store or hardware store when you want to save the data to NV portion of the nvSRAM. Only those stores will count for endurance.
Q:
Does disabling AutoStore set the chip's "dirty bit" thus causing a store when /HSB is asserted?
## No. As discussed earlier, the write latch is not set when you perform reads. I assume you are considering the internal write latch as "dirty bit" though I do not understand why you consider it so. The internal write latch is what prevents unwanted Store when there is no writes (and thus no change in the content). I assume you do not want Store to happen when HSB/ is asserted. If so, Store will not happen if you have performed only reads. However, if you have done writes, and do not want data to be Stored, you need to ensure HSB/ is not asserted. Or, you can leave HSB/ open.
If the dirty bit is set, are ALL bytes stored when /HSB is asserted, or only those bytes whose SRAM value differs from its stored value? “
## When Store happens it will happen to ALL bytes. The Store process consists of erasing the complete NV memory and storing the complete SRAM content into the NV memory.
Ravi, nvSRAM Apps Manager
你好，
您似乎正在调用内部“写锁存器”，每当写入发生时，它会被设置为脏位。这意味着您希望写入SRAM，但不希望在HSB/AISH声明时存储写入数据。如果这是你想要的，你有什么理由不能离开HSB/OPEN？
另外，为什么应用程序在每次上电时禁用AutoSt店。你可以做一次，做一个SW商店，让它承受功率循环。然后，只有当你做软件商店（HSW商店，如果HSB被断言当发生了写）时，商店才会发生。
我已经把我的答案放在你的问题中了。
问：CY14B256LA的数据表提到了20年的数据保持。其他NVSRAM产品列出100年。这是最近20年的存储操作，还是20年的芯片寿命？
在CY14B256LA中的20年数据保持在85℃下保证。在旧技术部分（0.8U部分）中的100年保证在5C。如果在相同的温度下进行比较，新部件有4倍于旧部件的数据保留。我们已经在App Note AN55 662中声明了这一点。
数据保留超过了部件的寿命。20年是积累的数据保留时间。
问：有没有办法从芯片上读取选项状态？
如果AutoStore被禁用了，那么禁用它再作为一个写入，就如同芯片的寿命一样吗？例如，如果包含芯片的设备在每次打开时自动禁用AutoStury，那么每个禁用的操作会通过占用1000000个存储计数来导致“耗尽”芯片吗？
不幸的是，无法检查一部分中的AutoStutial/Atdiable状态。
禁止存储不算作写入，也不影响1M存储计数。
AutoSturyAsabor或禁用是通过特定的读取顺序完成的。没有涉及写入周期。
读/写周期是对NVSRAM的SRAM部分进行的。SRAM具有无限的读/写持久性。
只有储存周期才算耐力。由于您禁用了AutoSt店，所以当您想将数据保存到NVSRAM的NV部分时，假设您将执行软件商店或硬件商店。只有那些商店才算耐用。
问：
禁用AutoSt店设置芯片的“脏位”，从而导致当/HSB被断言时存储吗？
正如前面所讨论的，在执行读取时，不设置写入锁存器。我认为你正在考虑内部写锁存为“肮脏的比特”，虽然我不明白为什么你这样认为。内部写锁存器在没有写入时防止不必要的存储（因此内容不改变）。我假设当HSB/AS被断言时，您不希望存储发生。如果是这样，如果您只执行读取，存储不会发生。但是，如果您已经完成了写入操作，并且不希望存储数据，则需要确保HSB/IS不被断言。或者，你可以离开HSB/OPEN。
如果设置了脏位，则当/HSB被断言时存储的所有字节，还是只有SRAM值与其存储值不同的字节？“
当存储发生时，它将发生在所有字节上。存储过程包括擦除完整的NV存储器并将完整的SRAM内容存储到NV存储器中。
Ravi，NVSRAMAPP经理
以上来自于百度翻译
以下为原文
Hi,
You seem to be calling the internal "write latch" which gets set whenever a write happens, as dirty bit. Which implies that you want to write into the SRAM but you do not want the written data to be Stored when HSB/ is asserted. If this is what you desire, is there any reason you cannot leave the HSB/ open?
Also, why is the application disabling AutoStore at every power up. You can do it once and do a SW store to make it endure power cycles. Fom then on, Stores will happen only when you do a software Store (HW store if HSB is asserted when write has happened).
I have placed my answers to your questions inline marked
##.
Q: The datasheet for the CY14B256LA mentions 20-year data retention. Other nvSRAM products list 100 years. Is that 20 years from the most recent store operation, or 20 years total over the life of the chip?
## The 20 year data retention in the CY14B256LA is guaranteed at 85C. The 100 years in the old technology part (0.8u parts) is guaranteed at 55C. If comparison is made at the same temperatures, the new parts have 4 times the data retention of the older part.. We have stated this in the app note AN55662.
## The data retention is over the life of the part. 20 years is the accumulated data retention time.
Q: Is there any way of reading the option status from the chip?
If AutoStore is disabled, does disabling it again count as a write as far as the life of the chip goes? For example, if the device containing the chip automatically disables AutoStore every time it turns on, does each disable operation contribute to "wearing out" the chip by eating into the 1,000,000 store count?
## Unfortunately there is no way to check the enable/disable status of AutoStore in a part.
## AutoStore disabling does not count as a write nor does it affect the 1M store count.
- Autostore anable or disable is done through a specific sequence of reads. There is no write cycle involved.
- Read/write cycles are done to the SRAM portion of the nvSRAM. The SRAM has infinite read/write endurance.
- Only Store cycles count for endurance. Since you are disabling autostore, I assume you will be performing a software store or hardware store when you want to save the data to NV portion of the nvSRAM. Only those stores will count for endurance.
Q:
Does disabling AutoStore set the chip's "dirty bit" thus causing a store when /HSB is asserted?
## No. As discussed earlier, the write latch is not set when you perform reads. I assume you are considering the internal write latch as "dirty bit" though I do not understand why you consider it so. The internal write latch is what prevents unwanted Store when there is no writes (and thus no change in the content). I assume you do not want Store to happen when HSB/ is asserted. If so, Store will not happen if you have performed only reads. However, if you have done writes, and do not want data to be Stored, you need to ensure HSB/ is not asserted. Or, you can leave HSB/ open.
If the dirty bit is set, are ALL bytes stored when /HSB is asserted, or only those bytes whose SRAM value differs from its stored value? “
## When Store happens it will happen to ALL bytes. The Store process consists of erasing the complete NV memory and storing the complete SRAM content into the NV memory.
Ravi, nvSRAM Apps Manager
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