循环模拟

如果没有改变，你为什么要重新合成设计呢？
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

If nothing changed, why did you resynthesize the design?
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

我做了......一百次......而且所有的时间都停留在同一个地方......状态|
编码-------------------------- s_init |
00 s_payload |
10 s_sendheader |
11 s_header |
01



以下为原文

I did... a hundred times... and all the time stucks at the same place....

State        | Encoding
--------------------------
s_init       | 00
s_payload    | 10
s_sendheader | 11
s_header     | 01

在您的原始帖子中，您说没有任何改变，但当您重新合成时，它会挂起。
如果没有改变，则不需要重新运行合成，因此看起来实际上已经发生了变化。
如果您无法提供更多详细信息，论坛将无法提供帮助。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

In your original post you said that nothing changed, but when you reran synthesis it hung.  Rerunning synthesis would not be required if nothing changed, so it would seem that something in fact has changed.  If you can't provide more details the forums won't be able to help.------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

我在testbench文件上改了一些东西，但后来我改回来......然后他说我的综合已经过时了，所以我重新合成了这个项目，并且它被困在那个地方。
我之前做过的一件事可能会导致一些错误..我安装了Modelsim来运行模拟，但我无法运行它，因为它说我的Unisim版本与ISE不同......类似的东西......
。



以下为原文

I changed something on the testbench file, but later I changed back... and then he said my synthesis was out of date, so I resynthetized the project, and it's stucked in that place. 
One thing that i had done before that maybe caused some bug.. I installed the Modelsim to run the simulation, but i was not able to run it because it said my version of Unisim was different from ISE... something like that...