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张亮

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[问答]

可重载系数FIR滤波器事件被断言

嗨,大家好,
我对具有可重载系数的FIR滤波器的行为有疑问。
在使用FIR编译器v6.3生成FIR滤波器之后,我尝试根据ds795_fir_compiler.pdf文档的第26页上的图10来模拟我的设计中的重载过程。
经过多次尝试后,我总是看到断言s_axis_config_tvalid(一个通道和一个系数集的过滤器)后,事件event_s_reload_tlast_unexpected被断言。
所以我切换到fir编译器本身生成的demo testbench。
如下图所示,可以观察到相同的行为。
所以我的问题是:这是核心的理想行为吗?
在生成核心时或者在控制协议中我是否误解了某些内容(但这是使用“官方”测试平台模拟的)?
在上述文档的第25页上,它表示事件接口的信号被视为错误或可以(可能)被忽略。
那么在断言s_axis_config_tvalid时,核心的rld_coeff tregister中的重载系数是否仍然加载到核心?

以上来自于谷歌翻译


以下为原文

Hi everyone,

i have question about the behaviour of a FIR filter with reloadable coefficients. After generating a FIR filter with the FIR compiler v6.3 i tried to simulate the reload process in my design according to Fig. 10 on page 26 of ds795_fir_compiler.pdf document. After several tries I always saw that after asserting s_axis_config_tvalid (a filter with one channel and one coefficient set) the event event_s_reload_tlast_unexpected is asserted. So i switched to the demo testbench generated by the fir compiler itself. As given in the Figure below the same behaviour can be observed.

So my questions are: Is this desired behaviour of the core? Did i misunderstand something when generating the core or maybe in the control protocol (but this is simulated with the "official" testbench)?

On page 25 of the mentioned document it says that the signals of the event interface are to be considered as errors or can (maybe) ignored. So are the reloaded coefficients in the rld_coeff tregister of the core nevertheless loaded to the core when asserting s_axis_config_tvalid?


回帖(3)

朱寅竹

2019-2-27 14:08:56
您是否在重新加载期间对最后一个(也是最后一个)系数进行了适当的断言?您是否正在观察系数重载顺序文本文件?
核心可能需要一个非显而易见的重载方案(即如果你有对称结构)
www.xilinx.com

以上来自于谷歌翻译


以下为原文

Are you asserting tlast appropriately on the last (and only the last) coefficient during reload?

Are you observing the coefficient reload order text file? The core may require a non-obvious reload scheme (i.e. if you have symmetric structure)www.xilinx.com
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张早

2019-2-27 14:17:46
嗨bwiec,
经过一些测试,我发现问题是数据包的同步。
我的方法是编写新系数,将它们设置为活动状态,并在需要时使用过滤器(并行中的一个)。
但是一种可能的情况是在此运行期间不需要滤波器(尽管它必须在硬件中可用以便以后运行,因此交错通道不是一种选择)并且滤波器保持不活动状态,直到必须再次写入新系数

这引起了另一个问题。
通过使用areset重置核心或将一些伪数据写入过滤器,只有两种可能性来重新设计新系数?!
我是否正确,只是覆盖已经写入的系数是不可能的?

以上来自于谷歌翻译


以下为原文

Hi bwiec,
 
after some more testing I found out that the problem was the synchronisation of the packets. My approach was to write new coefficients, set them active and use the filter (one of several in parallel) if needed. But one possible scenario is that the filter is not needed during this run (although it has to be available in hardware for a possible run later, hence interleaved channels are not an option) and the filter stays inactive until new coefficients have to be written again. This arises another question. There are only two posibilities to rerewrite new coefficients, either by resetting the core with areset or writing some dummy data to the filter?! Am I right that just overwriting the already written coefficients is not possible?
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宋晓媛

2019-2-27 14:22:57
你好,我是学生。
现在我设计了一个带有3个系数集的滤波器,我想在FIR Compiler 6.3中使用重载功能。系统可以在3个样本频率下工作,所以滤波器有3个系数集。
当选择频率样本时,我想重新加载系数。
系数在* .coe文件中,重新加载时,系数数据如何下降到核心?
以及如何计算重装槽?
我正在寻找你的回复!
我的邮箱是wuyanbei24@gmial.com。
谢谢!

以上来自于谷歌翻译


以下为原文

hello i am a student.
now i am design a filter wtih 3 coefficient sets,i want to use reload funtion in FIR Compiler 6.3 .the system can work in 3 sample feequency so the filter have 3 coefficeint sets. when chose the sample frequey, i want to reload the coefficeints.
the coefficeitns are in *.coe file, when reloading,how the coefficient data downto the core?
and how to caculae the reload slots?
 
i am looking forword your reply!
my mail is wuyanbei24@gmial.com.
thank you!
 
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